/*
 * Copyright (C) 1999-2013, Broadcom Corporation 
 *  
 *      Unless you and Broadcom execute a separate written software license 
 * agreement governing use of this software, this software is licensed to you 
 * under the terms of the GNU General Public License version 2 (the "GPL"), 
 * available at http://www.broadcom.com/licenses/GPLv2.php, with the 
 * following added to such license: 
 *  
 *      As a special exception, the copyright holders of this software give you 
 * permission to link this software with independent modules, and to copy and 
 * distribute the resulting executable under terms of your choice, provided that 
 * you also meet, for each linked independent module, the terms and conditions of 
 * the license of that module.  An independent module is a module which is not 
 * derived from this software.  The special exception does not apply to any 
 * modifications of the software. 
 *  
 *      Notwithstanding the above, under no circumstances may you combine this 
 * software in any way with any other Broadcom software provided under a license 
 * other than the GPL, without Broadcom's express prior written consent. 
 */
/***************************************************************************
 *     Copyright (c) 1999-2011, Broadcom Corporation
 *     All Rights Reserved
 *     Confidential Property of Broadcom Corporation
 *
 *
 * THIS SOFTWARE MAY ONLY BE USED SUBJECT TO AN EXECUTED SOFTWARE LICENSE
 * AGREEMENT  BETWEEN THE USER AND BROADCOM.  YOU HAVE NO RIGHT TO USE OR
 * EXPLOIT THIS MATERIAL EXCEPT SUBJECT TO THE TERMS OF SUCH AN AGREEMENT.
 *
 * $brcm_Workfile: local_memc_gen_0.h $
 * $brcm_Revision: cfe_bdvd_andover/1 $
 * $brcm_Date: 8/11/11 12:14p $
 *
 * Module Description:
 *                     DO NOT EDIT THIS FILE DIRECTLY
 *
 * This module was generated magically with RDB from a source description
 * file. You must edit the source file for changes to be made to this file.
 *
 *
 * Date:           Generated on         Wed Apr 20 11:41:03 2011
 *                 MD5 Checksum         f8b208c9aa3ad321e844687836b90339
 *
 * Compiled with:  RDB Utility          combo_header.pl
 *                 RDB Parser           3.0
 *                 unknown              unknown
 *                 Perl Interpreter     5.008008
 *                 Operating System     linux
 *
 * Revision History:
 *
 * $brcm_Log: /rockford/bsp/Shmoo/ddr40phy/include/local_memc_gen_0.h $
 * 
 * cfe_bdvd_andover/1   8/11/11 12:14p ckder
 * SWBLURAY-26789:[ see Broadcom Issue Tracking JIRA for more info ].
 * 
 * dev_cfe_bdvd_andover_SWBLURAY-26789/1   8/10/11 12:53p ckder
 * For TORONTO memc
 * 
 * Hydra_Software_Devel/4   4/21/11 11:13a yuxiaz
 * SWDTV-6742: Updated RDB files.
 *
 ***************************************************************************/

#ifndef BCHP_MEMC_GEN_0_H__
#define BCHP_MEMC_GEN_0_H__

/***************************************************************************
 *MEMC_GEN_0 - Memory Controller Testability Registers 0
 ***************************************************************************/
#define BCHP_MEMC_GEN_0_CORE_REV_ID              0x00000000 /* Memory-Controller-Core  Revision ID Register. */
#define BCHP_MEMC_GEN_0_BUS_PROTOCOL_VERSION     0x00000004 /* Memory-Controller-Core  Bus Protocol Version Register. */
#define BCHP_MEMC_GEN_0_MSA_MODE                 0x00000008 /* Memory Controller Memory-Soft-Access Mode Control Register */
#define BCHP_MEMC_GEN_0_MSA_STATUS               0x0000000c /* Memory Controller MSA Status Register */
#define BCHP_MEMC_GEN_0_MSA_CMD_TYPE             0x00000010 /* Memory Controller SCB Command Type Register */
#define BCHP_MEMC_GEN_0_MSA_CMD_ADDR             0x00000014 /* Memory Controller SCB Address Register */
#define BCHP_MEMC_GEN_0_MSA_WR_DATA0             0x00000018 /* Memory Controller MSA Write Data-0 Register */
#define BCHP_MEMC_GEN_0_MSA_WR_DATA1             0x0000001c /* Memory Controller MSA Write Data-1 Register */
#define BCHP_MEMC_GEN_0_MSA_WR_DATA2             0x00000020 /* Memory Controller MSA Write Data-2 Register */
#define BCHP_MEMC_GEN_0_MSA_WR_DATA3             0x00000024 /* Memory Controller MSA Write Data-3 Register */
#define BCHP_MEMC_GEN_0_MSA_WR_DATA4             0x00000028 /* Memory Controller MSA Write Data-4 Register */
#define BCHP_MEMC_GEN_0_MSA_WR_DATA5             0x0000002c /* Memory Controller MSA Write Data-5 Register */
#define BCHP_MEMC_GEN_0_MSA_WR_DATA6             0x00000030 /* Memory Controller MSA Write Data-6 Register */
#define BCHP_MEMC_GEN_0_MSA_WR_DATA7             0x00000034 /* Memory Controller MSA Write Data-7 Register */
#define BCHP_MEMC_GEN_0_MSA_DQM                  0x00000038 /* Memory Controller MSA DQM Register */
#define BCHP_MEMC_GEN_0_MSA_DALL                 0x0000003c /* Memory Controller MSA Block Write Data Register */
#define BCHP_MEMC_GEN_0_MSA_RD_DATA0             0x00000040 /* Memory Controller MSA Read Data-0 Register */
#define BCHP_MEMC_GEN_0_MSA_RD_DATA1             0x00000044 /* Memory Controller MSA Read Data-1 Register */
#define BCHP_MEMC_GEN_0_MSA_RD_DATA2             0x00000048 /* Memory Controller MSA Read Data-2 Register */
#define BCHP_MEMC_GEN_0_MSA_RD_DATA3             0x0000004c /* Memory Controller MSA Read Data-3 Register */
#define BCHP_MEMC_GEN_0_MSA_RD_DATA4             0x00000050 /* Memory Controller MSA Read Data-4 Register */
#define BCHP_MEMC_GEN_0_MSA_RD_DATA5             0x00000054 /* Memory Controller MSA Read Data-5 Register */
#define BCHP_MEMC_GEN_0_MSA_RD_DATA6             0x00000058 /* Memory Controller MSA Read Data-6 Register */
#define BCHP_MEMC_GEN_0_MSA_RD_DATA7             0x0000005c /* Memory Controller MSA Read Data-7 Register */
#define BCHP_MEMC_GEN_0_MSA_RD_DATA_CLR          0x00000060 /* MSA read data clear register. */
#define BCHP_MEMC_GEN_0_SCB_CRC_UNIT0_ENABLE     0x00000064 /* Unit0 SCB read/write data CRC enable register. */
#define BCHP_MEMC_GEN_0_SCB_CRC_UNIT0_0          0x00000068 /* Unit0 SCB read data CRC register. */
#define BCHP_MEMC_GEN_0_SCB_CRC_UNIT0_1          0x0000006c /* Unit0 SCB read data CRC register. */
#define BCHP_MEMC_GEN_0_SCB_CRC_UNIT0_2          0x00000070 /* Unit0 SCB read data CRC register. */
#define BCHP_MEMC_GEN_0_SCB_CRC_UNIT0_3          0x00000074 /* Unit0 SCB read data CRC register. */
#define BCHP_MEMC_GEN_0_SCB_CRC_UNIT0_4          0x00000078 /* Unit0 SCB read data CRC register. */
#define BCHP_MEMC_GEN_0_SCB_CRC_UNIT0_5          0x0000007c /* Unit0 SCB read data CRC register. */
#define BCHP_MEMC_GEN_0_SCB_CRC_UNIT0_6          0x00000080 /* Unit0 SCB read data CRC register. */
#define BCHP_MEMC_GEN_0_SCB_CRC_UNIT0_7          0x00000084 /* Unit0 SCB read data CRC register. */
#define BCHP_MEMC_GEN_0_SCB_CRC_UNIT0_8          0x00000088 /* Unit0 SCB read data CRC register. */
#define BCHP_MEMC_GEN_0_SCB_CRC_UNIT0_9          0x0000008c /* Unit0 SCB read data CRC register. */
#define BCHP_MEMC_GEN_0_SCB_CRC_UNIT0_10         0x00000090 /* Unit0 SCB read data CRC register. */
#define BCHP_MEMC_GEN_0_SCB_CRC_UNIT0_11         0x00000094 /* Unit0 SCB read data CRC register. */
#define BCHP_MEMC_GEN_0_SCB_CRC_UNIT0_12         0x00000098 /* Unit0 SCB read data CRC register. */
#define BCHP_MEMC_GEN_0_SCB_CRC_UNIT0_13         0x0000009c /* Unit0 SCB read data CRC register. */
#define BCHP_MEMC_GEN_0_SCB_CRC_UNIT0_14         0x000000a0 /* Unit0 SCB read data CRC register. */
#define BCHP_MEMC_GEN_0_SCB_CRC_UNIT0_15         0x000000a4 /* Unit0 SCB read data CRC register. */
#define BCHP_MEMC_GEN_0_SCB_CRC_UNIT1_ENABLE     0x000000a8 /* Unit1 SCB read/write data CRC enable register. */
#define BCHP_MEMC_GEN_0_SCB_CRC_UNIT1_0          0x000000ac /* Unit1 SCB read data CRC register. */
#define BCHP_MEMC_GEN_0_SCB_CRC_UNIT1_1          0x000000b0 /* Unit1 SCB read data CRC register. */
#define BCHP_MEMC_GEN_0_SCB_CRC_UNIT1_2          0x000000b4 /* Unit1 SCB read data CRC register. */
#define BCHP_MEMC_GEN_0_SCB_CRC_UNIT1_3          0x000000b8 /* Unit1 SCB read data CRC register. */
#define BCHP_MEMC_GEN_0_SCB_CRC_UNIT1_4          0x000000bc /* Unit1 SCB read data CRC register. */
#define BCHP_MEMC_GEN_0_SCB_CRC_UNIT1_5          0x000000c0 /* Unit1 SCB read data CRC register. */
#define BCHP_MEMC_GEN_0_SCB_CRC_UNIT1_6          0x000000c4 /* Unit1 SCB read data CRC register. */
#define BCHP_MEMC_GEN_0_SCB_CRC_UNIT1_7          0x000000c8 /* Unit1 SCB read data CRC register. */
#define BCHP_MEMC_GEN_0_SCB_CRC_UNIT1_8          0x000000cc /* Unit1 SCB read data CRC register. */
#define BCHP_MEMC_GEN_0_SCB_CRC_UNIT1_9          0x000000d0 /* Unit1 SCB read data CRC register. */
#define BCHP_MEMC_GEN_0_SCB_CRC_UNIT1_10         0x000000d4 /* Unit1 SCB read data CRC register. */
#define BCHP_MEMC_GEN_0_SCB_CRC_UNIT1_11         0x000000d8 /* Unit1 SCB read data CRC register. */
#define BCHP_MEMC_GEN_0_SCB_CRC_UNIT1_12         0x000000dc /* Unit1 SCB read data CRC register. */
#define BCHP_MEMC_GEN_0_SCB_CRC_UNIT1_13         0x000000e0 /* Unit1 SCB read data CRC register. */
#define BCHP_MEMC_GEN_0_SCB_CRC_UNIT1_14         0x000000e4 /* Unit1 SCB read data CRC register. */
#define BCHP_MEMC_GEN_0_SCB_CRC_UNIT1_15         0x000000e8 /* Unit1 SCB read data CRC register. */
#define BCHP_MEMC_GEN_0_DIS_CLIENT0_CMD          0x000000ec /* DDR interface stress client 0 command register. */
#define BCHP_MEMC_GEN_0_DIS_CLIENT0_START_ADDR   0x000000f0 /* DDR interface stress client 0 start address register. */
#define BCHP_MEMC_GEN_0_DIS_CLIENT0_END_ADDR     0x000000f4 /* DDR interface stress client 0 end address register. */
#define BCHP_MEMC_GEN_0_DIS_CLIENT0_DQM          0x000000f8 /* DDR interface stress client 0 DQM Register */
#define BCHP_MEMC_GEN_0_DIS_CLIENT0_TRIGGER      0x000000fc /* DDR interface stress client 0 start register. */
#define BCHP_MEMC_GEN_0_DIS_CLIENT0_STATUS       0x00000100 /* DDR interface stress client 0 status register. */
#define BCHP_MEMC_GEN_0_DIS_CLIENT0_STATUS_1     0x00000104 /* DDR interface stress client 0 status register. */
#define BCHP_MEMC_GEN_0_DIS_CLIENT0_STATUS_2     0x00000108 /* DDR interface stress client 0 status register. */
#define BCHP_MEMC_GEN_0_DIS_CLIENT0_STATUS_3     0x0000010c /* DDR interface stress client 0 status register. */
#define BCHP_MEMC_GEN_0_DIS_CLIENT0_STATUS_4     0x00000110 /* DDR interface stress client 0 status register. */
#define BCHP_MEMC_GEN_0_DIS_CLIENT0_STATUS_5     0x00000114 /* DDR interface stress client 0 status register. */
#define BCHP_MEMC_GEN_0_SM_TIMEOUT_INTR_INFO     0x00000144 /* MEMC State Machine Timeout Interrupt Information */
#define BCHP_MEMC_GEN_0_SM_TIMEOUT_INTR_WRITE_CLEAR 0x00000148 /* MEMC State Machine timeout interrupt write clear register */
#define BCHP_MEMC_GEN_0_SCB_NOREQ_INTR_INFO      0x0000014c /* MEMC Premature Request Withdrawal Interrupt Information */
#define BCHP_MEMC_GEN_0_SCB_NOREQ_INTR_WRITE_CLEAR 0x00000150 /* MEMC No Request interrupt write clear register */
#define BCHP_MEMC_GEN_0_SCB_CMD_INTR_INFO        0x00000154 /* MEMC Illegal Command Interrupt Information */
#define BCHP_MEMC_GEN_0_SCB_CMD_INTR_WRITE_CLEAR 0x00000158 /* MEMC Command interrupt write clear register */
#define BCHP_MEMC_GEN_0_SCB_NMB_INTR_INFO        0x0000015c /* MEMC Illegal NMB Interrupt Information */
#define BCHP_MEMC_GEN_0_SCB_NMB_INTR_WRITE_CLEAR 0x00000160 /* MEMC Illegal NMB interrupt write clear register */
#define BCHP_MEMC_GEN_0_SCB_START_ADDR_INTR_INFO 0x00000164 /* MEMC Illegal Start Address Interrupt Information */
#define BCHP_MEMC_GEN_0_SCB_START_ADDR_INTR_WRITE_CLEAR 0x00000168 /* MEMC Illegal Start Addr interrupt write clear register */
#define BCHP_MEMC_GEN_0_SCB_LAST_WRITE_ERROR_INFO 0x0000016c /* MEMC Missing SCB last write pulse error information */
#define BCHP_MEMC_GEN_0_SCB_LAST_WRITE_ERROR_WRITE_CLEAR 0x00000170 /* MEMC scb Missing SCB last write pulse write clear register */
#define BCHP_MEMC_GEN_0_CMD_TRACE_FIFO_MODE      0x00000174 /* Mode of the SCB command trace FIFO */
#define BCHP_MEMC_GEN_0_SEQ_CMD_DBG_0            0x00000178 /* Current DATA command pushed out from sequencer. */
#define BCHP_MEMC_GEN_0_SEQ_CMD_DBG_1            0x0000017c /* Current DATA command pushed out from sequencer. */
#define BCHP_MEMC_GEN_0_SEQ_CMD_DBG_2            0x00000180 /* Current DATA command pushed out from sequencer. */
#define BCHP_MEMC_GEN_0_SEQ_CMD_DBG_3            0x00000184 /* Current DATA command pushed out from sequencer. */
#define BCHP_MEMC_GEN_0_SEQ_CMD_DBG_4            0x00000188 /* Current DATA command pushed out from sequencer. */
#define BCHP_MEMC_GEN_0_SEQ_INPUT_DBG_INFO       0x0000018c /* Current input from CMD formatter to seq. */
#define BCHP_MEMC_GEN_0_MISC_SEQ_DBG_INFO        0x00000190 /* Status register of MISC command Sequencer. */
#define BCHP_MEMC_GEN_0_BIU_DBG_INFO             0x00000194 /* Debug information from BIU> */
#define BCHP_MEMC_GEN_0_SPARE_RO_3               0x00000198 /* Start Address corresponding to SCB command that occurred three commands earlier or end addr in case of PFRI. */
#define BCHP_MEMC_GEN_0_TP_ADRS                  0x0000019c /* Test Port Address Register */
#define BCHP_MEMC_GEN_0_TP_READ_DATA             0x000001a0 /* Test Port Data Read Register */
#define BCHP_MEMC_GEN_0_ARC_0_CNTRL              0x000001a4 /* Mode/Control register for Address Range Checker (ARC)-0 */
#define BCHP_MEMC_GEN_0_ARC_0_ADRS_RANGE_LOW     0x000001a8 /* Lower Address of the memory range for Address Range Checker (ARC)-0. */
#define BCHP_MEMC_GEN_0_ARC_0_ADRS_RANGE_HIGH    0x000001ac /* Higher Address of the memory range for Address Range Checker (ARC)-0. */
#define BCHP_MEMC_GEN_0_ARC_0_READ_RIGHTS_0      0x000001b0 /* Read access right of SCB clients 0 to 31 on Address Range Checker (ARC)-0 */
#define BCHP_MEMC_GEN_0_ARC_0_READ_RIGHTS_1      0x000001b4 /* Read access right of SCB clients 32 to 63 on Address Range Checker(ARC)-0 */
#define BCHP_MEMC_GEN_0_ARC_0_READ_RIGHTS_2      0x000001b8 /* Read access right of SCB clients 64 to 95 on Address Range Checker (ARC)-0 */
#define BCHP_MEMC_GEN_0_ARC_0_READ_RIGHTS_3      0x000001bc /* Read access right of SCB clients 96 to 127 on Address Range Checker(ARC)-0 */
#define BCHP_MEMC_GEN_0_ARC_0_WRITE_RIGHTS_0     0x000001c0 /* Write access right of SCB clients 0 to 31 on Address Range Checker(ARC)-0 */
#define BCHP_MEMC_GEN_0_ARC_0_WRITE_RIGHTS_1     0x000001c4 /* Write access right of SCB clients 32 to 63 on Address Range Checker(ARC)-0 */
#define BCHP_MEMC_GEN_0_ARC_0_WRITE_RIGHTS_2     0x000001c8 /* Write access right of SCB clients 0 to 31 on Address Range Checker(ARC)-0 */
#define BCHP_MEMC_GEN_0_ARC_0_WRITE_RIGHTS_3     0x000001cc /* Write access right of SCB clients 32 to 63 on Address Range Checker(ARC)-0 */
#define BCHP_MEMC_GEN_0_ARC_0_VIOLATION_INFO_START_ADDR 0x000001d0 /* Violating Command Start Address for Address Range Checker (ARC)-0 . */
#define BCHP_MEMC_GEN_0_ARC_0_VIOLATION_INFO_END_ADDR 0x000001d4 /* Violating Command End Address for Address Range Checker (ARC)-0 . */
#define BCHP_MEMC_GEN_0_ARC_0_VIOLATION_INFO_CMD 0x000001d8 /* Violating SCB client-ID & Command Type for Address Range Checker (ARC)-0 . */
#define BCHP_MEMC_GEN_0_ARC_0_VIOLATION_INFO_CLEAR 0x000001dc /* ARCH0 violation info write clear register */
#define BCHP_MEMC_GEN_0_ARC_1_CNTRL              0x000001e0 /* Mode/Control register for Address Range Checker (ARC)-1 */
#define BCHP_MEMC_GEN_0_ARC_1_ADRS_RANGE_LOW     0x000001e4 /* Lower Address of the memory range for Address Range Checker (ARC)-1. */
#define BCHP_MEMC_GEN_0_ARC_1_ADRS_RANGE_HIGH    0x000001e8 /* Higher Address of the memory range for Address Range Checker (ARC)-1. */
#define BCHP_MEMC_GEN_0_ARC_1_READ_RIGHTS_0      0x000001ec /* Read access right of SCB clients 0 to 31 on Address Range Checker (ARC)-1 */
#define BCHP_MEMC_GEN_0_ARC_1_READ_RIGHTS_1      0x000001f0 /* Read access right of SCB clients 32 to 63 on Address Range Checker(ARC)-1 */
#define BCHP_MEMC_GEN_0_ARC_1_READ_RIGHTS_2      0x000001f4 /* Read access right of SCB clients 64 to 95 on Address Range Checker (ARC)-1 */
#define BCHP_MEMC_GEN_0_ARC_1_READ_RIGHTS_3      0x000001f8 /* Read access right of SCB clients 96 to 127 on Address Range Checker(ARC)-1 */
#define BCHP_MEMC_GEN_0_ARC_1_WRITE_RIGHTS_0     0x000001fc /* Write access right of SCB clients 0 to 31 on Address Range Checker(ARC)-1 */
#define BCHP_MEMC_GEN_0_ARC_1_WRITE_RIGHTS_1     0x00000200 /* Write access right of SCB clients 32 to 63 on Address Range Checker(ARC)-1 */
#define BCHP_MEMC_GEN_0_ARC_1_WRITE_RIGHTS_2     0x00000204 /* Write access right of SCB clients 0 to 31 on Address Range Checker(ARC)-1 */
#define BCHP_MEMC_GEN_0_ARC_1_WRITE_RIGHTS_3     0x00000208 /* Write access right of SCB clients 32 to 63 on Address Range Checker(ARC)-1 */
#define BCHP_MEMC_GEN_0_ARC_1_VIOLATION_INFO_START_ADDR 0x0000020c /* Violating Command Start Address for Address Range Checker (ARC)-1 . */
#define BCHP_MEMC_GEN_0_ARC_1_VIOLATION_INFO_END_ADDR 0x00000210 /* Violating Command End Address for Address Range Checker (ARC)-1 . */
#define BCHP_MEMC_GEN_0_ARC_1_VIOLATION_INFO_CMD 0x00000214 /* Violating SCB client-ID & Command Type for Address Range Checker (ARC)-1 . */
#define BCHP_MEMC_GEN_0_ARC_1_VIOLATION_INFO_CLEAR 0x00000218 /* ARCH1 violation info write clear register */
#define BCHP_MEMC_GEN_0_ARC_2_CNTRL              0x0000021c /* Mode/Control register for Address Range Checker (ARC)-2 */
#define BCHP_MEMC_GEN_0_ARC_2_ADRS_RANGE_LOW     0x00000220 /* Lower Address of the memory range for Address Range Checker (ARC)-2. */
#define BCHP_MEMC_GEN_0_ARC_2_ADRS_RANGE_HIGH    0x00000224 /* Higher Address of the memory range for Address Range Checker (ARC)-2. */
#define BCHP_MEMC_GEN_0_ARC_2_READ_RIGHTS_0      0x00000228 /* Read access right of SCB clients 0 to 31 on Address Range Checker (ARC)-2 */
#define BCHP_MEMC_GEN_0_ARC_2_READ_RIGHTS_1      0x0000022c /* Read access right of SCB clients 32 to 63 on Address Range Checker(ARC)-2 */
#define BCHP_MEMC_GEN_0_ARC_2_READ_RIGHTS_2      0x00000230 /* Read access right of SCB clients 64 to 95 on Address Range Checker (ARC)-2 */
#define BCHP_MEMC_GEN_0_ARC_2_READ_RIGHTS_3      0x00000234 /* Read access right of SCB clients 96 to 127 on Address Range Checker(ARC)-2 */
#define BCHP_MEMC_GEN_0_ARC_2_WRITE_RIGHTS_0     0x00000238 /* Write access right of SCB clients 0 to 31 on Address Range Checker(ARC)-2 */
#define BCHP_MEMC_GEN_0_ARC_2_WRITE_RIGHTS_1     0x0000023c /* Write access right of SCB clients 32 to 63 on Address Range Checker(ARC)-2 */
#define BCHP_MEMC_GEN_0_ARC_2_WRITE_RIGHTS_2     0x00000240 /* Write access right of SCB clients 0 to 31 on Address Range Checker(ARC)-2 */
#define BCHP_MEMC_GEN_0_ARC_2_WRITE_RIGHTS_3     0x00000244 /* Write access right of SCB clients 32 to 63 on Address Range Checker(ARC)-2 */
#define BCHP_MEMC_GEN_0_ARC_2_VIOLATION_INFO_START_ADDR 0x00000248 /* Violating Command Start Address for Address Range Checker (ARC)-2 . */
#define BCHP_MEMC_GEN_0_ARC_2_VIOLATION_INFO_END_ADDR 0x0000024c /* Violating Command End Address for Address Range Checker (ARC)-2 . */
#define BCHP_MEMC_GEN_0_ARC_2_VIOLATION_INFO_CMD 0x00000250 /* Violating SCB client-ID & Command Type for Address Range Checker (ARC)-2 . */
#define BCHP_MEMC_GEN_0_ARC_2_VIOLATION_INFO_CLEAR 0x00000254 /* ARCH2 violation info write clear register */
#define BCHP_MEMC_GEN_0_ARC_3_CNTRL              0x00000258 /* Mode/Control register for Address Range Checker (ARC)-3 */
#define BCHP_MEMC_GEN_0_ARC_3_ADRS_RANGE_LOW     0x0000025c /* Lower Address of the memory range for Address Range Checker (ARC)-3. */
#define BCHP_MEMC_GEN_0_ARC_3_ADRS_RANGE_HIGH    0x00000260 /* Higher Address of the memory range for Address Range Checker (ARC)-3. */
#define BCHP_MEMC_GEN_0_ARC_3_READ_RIGHTS_0      0x00000264 /* Read access right of SCB clients 0 to 31 on Address Range Checker (ARC)-3 */
#define BCHP_MEMC_GEN_0_ARC_3_READ_RIGHTS_1      0x00000268 /* Read access right of SCB clients 32 to 63 on Address Range Checker(ARC)-3 */
#define BCHP_MEMC_GEN_0_ARC_3_READ_RIGHTS_2      0x0000026c /* Read access right of SCB clients 64 to 95 on Address Range Checker (ARC)-3 */
#define BCHP_MEMC_GEN_0_ARC_3_READ_RIGHTS_3      0x00000270 /* Read access right of SCB clients 96 to 127 on Address Range Checker(ARC)-3 */
#define BCHP_MEMC_GEN_0_ARC_3_WRITE_RIGHTS_0     0x00000274 /* Write access right of SCB clients 0 to 31 on Address Range Checker(ARC)-3 */
#define BCHP_MEMC_GEN_0_ARC_3_WRITE_RIGHTS_1     0x00000278 /* Write access right of SCB clients 32 to 63 on Address Range Checker(ARC)-3 */
#define BCHP_MEMC_GEN_0_ARC_3_WRITE_RIGHTS_2     0x0000027c /* Write access right of SCB clients 0 to 31 on Address Range Checker(ARC)-3 */
#define BCHP_MEMC_GEN_0_ARC_3_WRITE_RIGHTS_3     0x00000280 /* Write access right of SCB clients 32 to 63 on Address Range Checker(ARC)-3 */
#define BCHP_MEMC_GEN_0_ARC_3_VIOLATION_INFO_START_ADDR 0x00000284 /* Violating Command Start Address for Address Range Checker (ARC)-3 . */
#define BCHP_MEMC_GEN_0_ARC_3_VIOLATION_INFO_END_ADDR 0x00000288 /* Violating Command End Address for Address Range Checker (ARC)-3 . */
#define BCHP_MEMC_GEN_0_ARC_3_VIOLATION_INFO_CMD 0x0000028c /* Violating SCB client-ID & Command Type for Address Range Checker (ARC)-3 . */
#define BCHP_MEMC_GEN_0_ARC_3_VIOLATION_INFO_CLEAR 0x00000290 /* ARCH3 violation info write clear register */
#define BCHP_MEMC_GEN_0_MEMC64_MBIST_TM_CNTRL    0x00000294 /* MEMC64_0 MBIST TM Control Register */
#define BCHP_MEMC_GEN_0_DUMMY_CMD                0x00000298 /* Dummy SCB Command */
#define BCHP_MEMC_GEN_0_DUMMY_REQ_CNT_CPU0       0x0000029c /* Dummy Request Count CPU0 */
#define BCHP_MEMC_GEN_0_DUMMY_REQ_CNT_CPU1       0x000002a0 /* Dummy Request Count CPU1 */
#define BCHP_MEMC_GEN_0_CNTR_RST                 0x000002a4 /* Reset Request Counters */
#define BCHP_MEMC_GEN_0_CNTR_FREEZE              0x000002a8 /* Freeze Request Counters */
#define BCHP_MEMC_GEN_0_VAL_REQ_CNT_CPU0         0x000002ac /* Valid Request Count CPU0 */
#define BCHP_MEMC_GEN_0_VAL_REQ_CNT_CPU1         0x000002b0 /* Valid Request Count CPU1 */
#define BCHP_MEMC_GEN_0_PFRI_0_PAGE_BRK_INTR_INFO_0 0x000002b4 /* PFRI Page Break Interrupt Information Register 0 for lient 120 */
#define BCHP_MEMC_GEN_0_PFRI_0_PAGE_BRK_INTR_INFO_1 0x000002b8 /* PFRI Page Break Interrupt Information Register 1 for client 120 */
#define BCHP_MEMC_GEN_0_PFRI_0_VIOLATION_INFO_WRITE_CLEAR 0x000002bc /* PFRI violation info write clear register for client 120 */
#define BCHP_MEMC_GEN_0_PFRI_1_PAGE_BRK_INTR_INFO_0 0x000002c0 /* PFRI Page Break Interrupt Information Register 0 for client 121 */
#define BCHP_MEMC_GEN_0_PFRI_1_PAGE_BRK_INTR_INFO_1 0x000002c4 /* PFRI Page Break Interrupt Information Register 1 for client 121 */
#define BCHP_MEMC_GEN_0_PFRI_1_VIOLATION_INFO_WRITE_CLEAR 0x000002c8 /* PFRI violation info write clear register for client 121 */
#define BCHP_MEMC_GEN_0_PFRI_2_PAGE_BRK_INTR_INFO_0 0x000002cc /* PFRI Page Break Interrupt Information Register 0 for client 122 */
#define BCHP_MEMC_GEN_0_PFRI_2_PAGE_BRK_INTR_INFO_1 0x000002d0 /* PFRI Page Break Interrupt Information Register 1 for client 122 */
#define BCHP_MEMC_GEN_0_PFRI_2_VIOLATION_INFO_WRITE_CLEAR 0x000002d4 /* PFRI violation info write clear register client 122 */
#define BCHP_MEMC_GEN_0_PFRI_3_PAGE_BRK_INTR_INFO_0 0x000002d8 /* PFRI Page Break Interrupt Information Register 0 for client 123 */
#define BCHP_MEMC_GEN_0_PFRI_3_PAGE_BRK_INTR_INFO_1 0x000002dc /* PFRI Page Break Interrupt Information Register 1 for client 123 */
#define BCHP_MEMC_GEN_0_PFRI_3_VIOLATION_INFO_WRITE_CLEAR 0x000002e0 /* PFRI violation info write clear register for client 123 */
#define BCHP_MEMC_GEN_0_LMB_ADDRESS_ERROR_INFO   0x000002e4 /* LMB un-aligned address error information register */
#define BCHP_MEMC_GEN_0_LMB_ADDRESS_ERROR_INFO_WRITE_CLEAR 0x000002e8 /* LMB un-aligned address error info write clear register */
#define BCHP_MEMC_GEN_0_PFRI_0_LADDR_FIFO_DEPTH_COUNT 0x000002ec /* PFRI_0 Laddr fifo depth count register */
#define BCHP_MEMC_GEN_0_PFRI_1_LADDR_FIFO_DEPTH_COUNT 0x000002f0 /* PFRI_1 Laddr fifo depth count register */
#define BCHP_MEMC_GEN_0_PFRI_2_LADDR_FIFO_DEPTH_COUNT 0x000002f4 /* PFRI_2 Laddr fifo depth count register */
#define BCHP_MEMC_GEN_0_PFRI_3_LADDR_FIFO_DEPTH_COUNT 0x000002f8 /* PFRI_3 Laddr fifo depth count register */
#define BCHP_MEMC_GEN_0_PFRI_0_TEST_CLIENT_COMMAND 0x000002fc /* PFRI_0 test client command register */
#define BCHP_MEMC_GEN_0_PFRI_1_TEST_CLIENT_COMMAND 0x00000300 /* PFRI_1 test client command register */
#define BCHP_MEMC_GEN_0_PFRI_2_TEST_CLIENT_COMMAND 0x00000304 /* PFRI_2 test client command register */
#define BCHP_MEMC_GEN_0_PFRI_3_TEST_CLIENT_COMMAND 0x00000308 /* PFRI_3 test client command register */
#define BCHP_MEMC_GEN_0_PFRI_0_TEST_CLIENT_BUSY_FLAG 0x0000030c /* PFRI_0 test client busy flag register */
#define BCHP_MEMC_GEN_0_PFRI_1_TEST_CLIENT_BUSY_FLAG 0x00000310 /* PFRI_1 test client busy flag register */
#define BCHP_MEMC_GEN_0_PFRI_2_TEST_CLIENT_BUSY_FLAG 0x00000314 /* PFRI_2 test client busy flag register */
#define BCHP_MEMC_GEN_0_PFRI_3_TEST_CLIENT_BUSY_FLAG 0x00000318 /* PFRI_3 test client busy flag register */
#define BCHP_MEMC_GEN_0_SPARE_1                  0x0000031c /* Spare Register 1 . */
#define BCHP_MEMC_GEN_0_SPARE_2                  0x00000320 /* Spare Register 2 . */
#define BCHP_MEMC_GEN_0_SPARE_RO_1               0x00000324 /* Read only Spare Register 0 . */
#define BCHP_MEMC_GEN_0_SPARE_RO_2               0x00000328 /* Read only Spare Register 1 . */
#define BCHP_MEMC_GEN_0_TP_CORE_SEL              0x0000032c /* Test port selection register. */
#define BCHP_MEMC_GEN_0_PFRI_4_PAGE_BRK_INTR_INFO_0 0x00000330 /* PFRI Page Break Interrupt Information Register 0 for client 116 */
#define BCHP_MEMC_GEN_0_PFRI_4_PAGE_BRK_INTR_INFO_1 0x00000334 /* PFRI Page Break Interrupt Information Register 1 for client 116 */
#define BCHP_MEMC_GEN_0_PFRI_4_VIOLATION_INFO_WRITE_CLEAR 0x00000338 /* PFRI violation info write clear register for client 116 */
#define BCHP_MEMC_GEN_0_PFRI_4_LADDR_FIFO_DEPTH_COUNT 0x0000033c /* PFRI_4 Laddr fifo depth count register */
#define BCHP_MEMC_GEN_0_PFRI_4_TEST_CLIENT_COMMAND 0x00000340 /* PFRI_4 test client command register */
#define BCHP_MEMC_GEN_0_PFRI_4_TEST_CLIENT_BUSY_FLAG 0x00000344 /* PFRI_4 test client busy flag register */
#define BCHP_MEMC_GEN_0_MISC_BIU_MSA_REG         0x00000348 /* PFRI_4 test client busy flag register */
#define BCHP_MEMC_GEN_0_DIS_CLIENT1_CMD          0x000003a8 /* DDR interface stress client 1 command register. */
#define BCHP_MEMC_GEN_0_DIS_CLIENT1_START_ADDR   0x000003ac /* DDR interface stress client 1 start address register. */
#define BCHP_MEMC_GEN_0_DIS_CLIENT1_END_ADDR     0x000003b0 /* DDR interface stress client 1 end address register. */
#define BCHP_MEMC_GEN_0_DIS_CLIENT1_DQM          0x000003b4 /* DDR interface stress client 1 DQM Register */
#define BCHP_MEMC_GEN_0_DIS_CLIENT1_TRIGGER      0x000003b8 /* DDR interface stress client 1 start register. */
#define BCHP_MEMC_GEN_0_DIS_CLIENT1_STATUS       0x000003bc /* DDR interface stress client 1 status register. */
#define BCHP_MEMC_GEN_0_DIS_CLIENT1_STATUS_1     0x000003c0 /* DDR interface stress client 1 status register. */
#define BCHP_MEMC_GEN_0_DIS_CLIENT1_STATUS_2     0x000003c4 /* DDR interface stress client 1 status register. */
#define BCHP_MEMC_GEN_0_DIS_CLIENT1_STATUS_3     0x000003c8 /* DDR interface stress client 1 status register. */
#define BCHP_MEMC_GEN_0_DIS_CLIENT1_STATUS_4     0x000003cc /* DDR interface stress client 1 status register. */
#define BCHP_MEMC_GEN_0_DIS_CLIENT1_STATUS_5     0x000003d0 /* DDR interface stress client 1 status register. */

/***************************************************************************
 *CORE_REV_ID - Memory-Controller-Core  Revision ID Register.
 ***************************************************************************/
/* MEMC_GEN_0 :: CORE_REV_ID :: reserved0 [31:16] */
#define BCHP_MEMC_GEN_0_CORE_REV_ID_reserved0_MASK                 0xffff0000
#define BCHP_MEMC_GEN_0_CORE_REV_ID_reserved0_SHIFT                16

/* MEMC_GEN_0 :: CORE_REV_ID :: ARCH_REV_ID [15:12] */
#define BCHP_MEMC_GEN_0_CORE_REV_ID_ARCH_REV_ID_MASK               0x0000f000
#define BCHP_MEMC_GEN_0_CORE_REV_ID_ARCH_REV_ID_SHIFT              12
#define BCHP_MEMC_GEN_0_CORE_REV_ID_ARCH_REV_ID_DEFAULT            10

/* MEMC_GEN_0 :: CORE_REV_ID :: CFG_REV_ID [11:08] */
#define BCHP_MEMC_GEN_0_CORE_REV_ID_CFG_REV_ID_MASK                0x00000f00
#define BCHP_MEMC_GEN_0_CORE_REV_ID_CFG_REV_ID_SHIFT               8
#define BCHP_MEMC_GEN_0_CORE_REV_ID_CFG_REV_ID_DEFAULT             0

/* MEMC_GEN_0 :: CORE_REV_ID :: ALL_LAYER_ID [07:04] */
#define BCHP_MEMC_GEN_0_CORE_REV_ID_ALL_LAYER_ID_MASK              0x000000f0
#define BCHP_MEMC_GEN_0_CORE_REV_ID_ALL_LAYER_ID_SHIFT             4
#define BCHP_MEMC_GEN_0_CORE_REV_ID_ALL_LAYER_ID_DEFAULT           0

/* MEMC_GEN_0 :: CORE_REV_ID :: METAL_LAYER_ID [03:00] */
#define BCHP_MEMC_GEN_0_CORE_REV_ID_METAL_LAYER_ID_MASK            0x0000000f
#define BCHP_MEMC_GEN_0_CORE_REV_ID_METAL_LAYER_ID_SHIFT           0
#define BCHP_MEMC_GEN_0_CORE_REV_ID_METAL_LAYER_ID_DEFAULT         0

/***************************************************************************
 *BUS_PROTOCOL_VERSION - Memory-Controller-Core  Bus Protocol Version Register.
 ***************************************************************************/
/* MEMC_GEN_0 :: BUS_PROTOCOL_VERSION :: DRAM_MAP_VERSION [31:24] */
#define BCHP_MEMC_GEN_0_BUS_PROTOCOL_VERSION_DRAM_MAP_VERSION_MASK 0xff000000
#define BCHP_MEMC_GEN_0_BUS_PROTOCOL_VERSION_DRAM_MAP_VERSION_SHIFT 24
#define BCHP_MEMC_GEN_0_BUS_PROTOCOL_VERSION_DRAM_MAP_VERSION_DEFAULT 32

/* MEMC_GEN_0 :: BUS_PROTOCOL_VERSION :: LMB_BUS_VERSION [23:16] */
#define BCHP_MEMC_GEN_0_BUS_PROTOCOL_VERSION_LMB_BUS_VERSION_MASK  0x00ff0000
#define BCHP_MEMC_GEN_0_BUS_PROTOCOL_VERSION_LMB_BUS_VERSION_SHIFT 16
#define BCHP_MEMC_GEN_0_BUS_PROTOCOL_VERSION_LMB_BUS_VERSION_DEFAULT 21

/* MEMC_GEN_0 :: BUS_PROTOCOL_VERSION :: PFRI_BUS_VERSION [15:08] */
#define BCHP_MEMC_GEN_0_BUS_PROTOCOL_VERSION_PFRI_BUS_VERSION_MASK 0x0000ff00
#define BCHP_MEMC_GEN_0_BUS_PROTOCOL_VERSION_PFRI_BUS_VERSION_SHIFT 8
#define BCHP_MEMC_GEN_0_BUS_PROTOCOL_VERSION_PFRI_BUS_VERSION_DEFAULT 48

/* MEMC_GEN_0 :: BUS_PROTOCOL_VERSION :: SCB_BUS_VERSION [07:00] */
#define BCHP_MEMC_GEN_0_BUS_PROTOCOL_VERSION_SCB_BUS_VERSION_MASK  0x000000ff
#define BCHP_MEMC_GEN_0_BUS_PROTOCOL_VERSION_SCB_BUS_VERSION_SHIFT 0
#define BCHP_MEMC_GEN_0_BUS_PROTOCOL_VERSION_SCB_BUS_VERSION_DEFAULT 66

/***************************************************************************
 *MSA_MODE - Memory Controller Memory-Soft-Access Mode Control Register
 ***************************************************************************/
/* MEMC_GEN_0 :: MSA_MODE :: reserved0 [31:03] */
#define BCHP_MEMC_GEN_0_MSA_MODE_reserved0_MASK                    0xfffffff8
#define BCHP_MEMC_GEN_0_MSA_MODE_reserved0_SHIFT                   3

/* MEMC_GEN_0 :: MSA_MODE :: CHKSM_RD [02:02] */
#define BCHP_MEMC_GEN_0_MSA_MODE_CHKSM_RD_MASK                     0x00000004
#define BCHP_MEMC_GEN_0_MSA_MODE_CHKSM_RD_SHIFT                    2
#define BCHP_MEMC_GEN_0_MSA_MODE_CHKSM_RD_DEFAULT                  0

/* MEMC_GEN_0 :: MSA_MODE :: PRBS_DQM [01:01] */
#define BCHP_MEMC_GEN_0_MSA_MODE_PRBS_DQM_MASK                     0x00000002
#define BCHP_MEMC_GEN_0_MSA_MODE_PRBS_DQM_SHIFT                    1
#define BCHP_MEMC_GEN_0_MSA_MODE_PRBS_DQM_DEFAULT                  0

/* MEMC_GEN_0 :: MSA_MODE :: PRBS_WR [00:00] */
#define BCHP_MEMC_GEN_0_MSA_MODE_PRBS_WR_MASK                      0x00000001
#define BCHP_MEMC_GEN_0_MSA_MODE_PRBS_WR_SHIFT                     0
#define BCHP_MEMC_GEN_0_MSA_MODE_PRBS_WR_DEFAULT                   0

/***************************************************************************
 *MSA_STATUS - Memory Controller MSA Status Register
 ***************************************************************************/
/* MEMC_GEN_0 :: MSA_STATUS :: reserved0 [31:04] */
#define BCHP_MEMC_GEN_0_MSA_STATUS_reserved0_MASK                  0xfffffff0
#define BCHP_MEMC_GEN_0_MSA_STATUS_reserved0_SHIFT                 4

/* MEMC_GEN_0 :: MSA_STATUS :: FIFO_FULL [03:03] */
#define BCHP_MEMC_GEN_0_MSA_STATUS_FIFO_FULL_MASK                  0x00000008
#define BCHP_MEMC_GEN_0_MSA_STATUS_FIFO_FULL_SHIFT                 3
#define BCHP_MEMC_GEN_0_MSA_STATUS_FIFO_FULL_DEFAULT               0
#define BCHP_MEMC_GEN_0_MSA_STATUS_FIFO_FULL_YES                   1
#define BCHP_MEMC_GEN_0_MSA_STATUS_FIFO_FULL_NO                    0

/* MEMC_GEN_0 :: MSA_STATUS :: FIFO_EMPTY [02:02] */
#define BCHP_MEMC_GEN_0_MSA_STATUS_FIFO_EMPTY_MASK                 0x00000004
#define BCHP_MEMC_GEN_0_MSA_STATUS_FIFO_EMPTY_SHIFT                2
#define BCHP_MEMC_GEN_0_MSA_STATUS_FIFO_EMPTY_DEFAULT              0
#define BCHP_MEMC_GEN_0_MSA_STATUS_FIFO_EMPTY_YES                  1
#define BCHP_MEMC_GEN_0_MSA_STATUS_FIFO_EMPTY_NO                   0

/* MEMC_GEN_0 :: MSA_STATUS :: T_LOCK [01:01] */
#define BCHP_MEMC_GEN_0_MSA_STATUS_T_LOCK_MASK                     0x00000002
#define BCHP_MEMC_GEN_0_MSA_STATUS_T_LOCK_SHIFT                    1
#define BCHP_MEMC_GEN_0_MSA_STATUS_T_LOCK_DEFAULT                  0
#define BCHP_MEMC_GEN_0_MSA_STATUS_T_LOCK_YES                      1
#define BCHP_MEMC_GEN_0_MSA_STATUS_T_LOCK_NO                       0

/* MEMC_GEN_0 :: MSA_STATUS :: BUSY [00:00] */
#define BCHP_MEMC_GEN_0_MSA_STATUS_BUSY_MASK                       0x00000001
#define BCHP_MEMC_GEN_0_MSA_STATUS_BUSY_SHIFT                      0
#define BCHP_MEMC_GEN_0_MSA_STATUS_BUSY_DEFAULT                    0
#define BCHP_MEMC_GEN_0_MSA_STATUS_BUSY_YES                        1
#define BCHP_MEMC_GEN_0_MSA_STATUS_BUSY_NO                         0

/***************************************************************************
 *MSA_CMD_TYPE - Memory Controller SCB Command Type Register
 ***************************************************************************/
/* MEMC_GEN_0 :: MSA_CMD_TYPE :: reserved0 [31:22] */
#define BCHP_MEMC_GEN_0_MSA_CMD_TYPE_reserved0_MASK                0xffc00000
#define BCHP_MEMC_GEN_0_MSA_CMD_TYPE_reserved0_SHIFT               22

/* MEMC_GEN_0 :: MSA_CMD_TYPE :: NMB [21:12] */
#define BCHP_MEMC_GEN_0_MSA_CMD_TYPE_NMB_MASK                      0x003ff000
#define BCHP_MEMC_GEN_0_MSA_CMD_TYPE_NMB_SHIFT                     12
#define BCHP_MEMC_GEN_0_MSA_CMD_TYPE_NMB_DEFAULT                   0

/* MEMC_GEN_0 :: MSA_CMD_TYPE :: reserved1 [11:09] */
#define BCHP_MEMC_GEN_0_MSA_CMD_TYPE_reserved1_MASK                0x00000e00
#define BCHP_MEMC_GEN_0_MSA_CMD_TYPE_reserved1_SHIFT               9

/* MEMC_GEN_0 :: MSA_CMD_TYPE :: REQ_TYPE [08:00] */
#define BCHP_MEMC_GEN_0_MSA_CMD_TYPE_REQ_TYPE_MASK                 0x000001ff
#define BCHP_MEMC_GEN_0_MSA_CMD_TYPE_REQ_TYPE_SHIFT                0
#define BCHP_MEMC_GEN_0_MSA_CMD_TYPE_REQ_TYPE_DEFAULT              0

/***************************************************************************
 *MSA_CMD_ADDR - Memory Controller SCB Address Register
 ***************************************************************************/
/* MEMC_GEN_0 :: MSA_CMD_ADDR :: reserved0 [31:29] */
#define BCHP_MEMC_GEN_0_MSA_CMD_ADDR_reserved0_MASK                0xe0000000
#define BCHP_MEMC_GEN_0_MSA_CMD_ADDR_reserved0_SHIFT               29

/* MEMC_GEN_0 :: MSA_CMD_ADDR :: ADDR [28:00] */
#define BCHP_MEMC_GEN_0_MSA_CMD_ADDR_ADDR_MASK                     0x1fffffff
#define BCHP_MEMC_GEN_0_MSA_CMD_ADDR_ADDR_SHIFT                    0
#define BCHP_MEMC_GEN_0_MSA_CMD_ADDR_ADDR_DEFAULT                  0

/***************************************************************************
 *MSA_WR_DATA0 - Memory Controller MSA Write Data-0 Register
 ***************************************************************************/
/* MEMC_GEN_0 :: MSA_WR_DATA0 :: Data [31:00] */
#define BCHP_MEMC_GEN_0_MSA_WR_DATA0_Data_MASK                     0xffffffff
#define BCHP_MEMC_GEN_0_MSA_WR_DATA0_Data_SHIFT                    0

/***************************************************************************
 *MSA_WR_DATA1 - Memory Controller MSA Write Data-1 Register
 ***************************************************************************/
/* MEMC_GEN_0 :: MSA_WR_DATA1 :: Data [31:00] */
#define BCHP_MEMC_GEN_0_MSA_WR_DATA1_Data_MASK                     0xffffffff
#define BCHP_MEMC_GEN_0_MSA_WR_DATA1_Data_SHIFT                    0

/***************************************************************************
 *MSA_WR_DATA2 - Memory Controller MSA Write Data-2 Register
 ***************************************************************************/
/* MEMC_GEN_0 :: MSA_WR_DATA2 :: Data [31:00] */
#define BCHP_MEMC_GEN_0_MSA_WR_DATA2_Data_MASK                     0xffffffff
#define BCHP_MEMC_GEN_0_MSA_WR_DATA2_Data_SHIFT                    0

/***************************************************************************
 *MSA_WR_DATA3 - Memory Controller MSA Write Data-3 Register
 ***************************************************************************/
/* MEMC_GEN_0 :: MSA_WR_DATA3 :: Data [31:00] */
#define BCHP_MEMC_GEN_0_MSA_WR_DATA3_Data_MASK                     0xffffffff
#define BCHP_MEMC_GEN_0_MSA_WR_DATA3_Data_SHIFT                    0

/***************************************************************************
 *MSA_WR_DATA4 - Memory Controller MSA Write Data-4 Register
 ***************************************************************************/
/* MEMC_GEN_0 :: MSA_WR_DATA4 :: Data [31:00] */
#define BCHP_MEMC_GEN_0_MSA_WR_DATA4_Data_MASK                     0xffffffff
#define BCHP_MEMC_GEN_0_MSA_WR_DATA4_Data_SHIFT                    0

/***************************************************************************
 *MSA_WR_DATA5 - Memory Controller MSA Write Data-5 Register
 ***************************************************************************/
/* MEMC_GEN_0 :: MSA_WR_DATA5 :: Data [31:00] */
#define BCHP_MEMC_GEN_0_MSA_WR_DATA5_Data_MASK                     0xffffffff
#define BCHP_MEMC_GEN_0_MSA_WR_DATA5_Data_SHIFT                    0

/***************************************************************************
 *MSA_WR_DATA6 - Memory Controller MSA Write Data-6 Register
 ***************************************************************************/
/* MEMC_GEN_0 :: MSA_WR_DATA6 :: Data [31:00] */
#define BCHP_MEMC_GEN_0_MSA_WR_DATA6_Data_MASK                     0xffffffff
#define BCHP_MEMC_GEN_0_MSA_WR_DATA6_Data_SHIFT                    0

/***************************************************************************
 *MSA_WR_DATA7 - Memory Controller MSA Write Data-7 Register
 ***************************************************************************/
/* MEMC_GEN_0 :: MSA_WR_DATA7 :: Data [31:00] */
#define BCHP_MEMC_GEN_0_MSA_WR_DATA7_Data_MASK                     0xffffffff
#define BCHP_MEMC_GEN_0_MSA_WR_DATA7_Data_SHIFT                    0

/***************************************************************************
 *MSA_DQM - Memory Controller MSA DQM Register
 ***************************************************************************/
/* MEMC_GEN_0 :: MSA_DQM :: MSA_Data [31:00] */
#define BCHP_MEMC_GEN_0_MSA_DQM_MSA_Data_MASK                      0xffffffff
#define BCHP_MEMC_GEN_0_MSA_DQM_MSA_Data_SHIFT                     0
#define BCHP_MEMC_GEN_0_MSA_DQM_MSA_Data_DEFAULT                   0

/***************************************************************************
 *MSA_DALL - Memory Controller MSA Block Write Data Register
 ***************************************************************************/
/* MEMC_GEN_0 :: MSA_DALL :: Data [31:00] */
#define BCHP_MEMC_GEN_0_MSA_DALL_Data_MASK                         0xffffffff
#define BCHP_MEMC_GEN_0_MSA_DALL_Data_SHIFT                        0
#define BCHP_MEMC_GEN_0_MSA_DALL_Data_DEFAULT                      0

/***************************************************************************
 *MSA_RD_DATA0 - Memory Controller MSA Read Data-0 Register
 ***************************************************************************/
/* MEMC_GEN_0 :: MSA_RD_DATA0 :: Data [31:00] */
#define BCHP_MEMC_GEN_0_MSA_RD_DATA0_Data_MASK                     0xffffffff
#define BCHP_MEMC_GEN_0_MSA_RD_DATA0_Data_SHIFT                    0
#define BCHP_MEMC_GEN_0_MSA_RD_DATA0_Data_DEFAULT                  0

/***************************************************************************
 *MSA_RD_DATA1 - Memory Controller MSA Read Data-1 Register
 ***************************************************************************/
/* MEMC_GEN_0 :: MSA_RD_DATA1 :: Data [31:00] */
#define BCHP_MEMC_GEN_0_MSA_RD_DATA1_Data_MASK                     0xffffffff
#define BCHP_MEMC_GEN_0_MSA_RD_DATA1_Data_SHIFT                    0
#define BCHP_MEMC_GEN_0_MSA_RD_DATA1_Data_DEFAULT                  0

/***************************************************************************
 *MSA_RD_DATA2 - Memory Controller MSA Read Data-2 Register
 ***************************************************************************/
/* MEMC_GEN_0 :: MSA_RD_DATA2 :: Data [31:00] */
#define BCHP_MEMC_GEN_0_MSA_RD_DATA2_Data_MASK                     0xffffffff
#define BCHP_MEMC_GEN_0_MSA_RD_DATA2_Data_SHIFT                    0
#define BCHP_MEMC_GEN_0_MSA_RD_DATA2_Data_DEFAULT                  0

/***************************************************************************
 *MSA_RD_DATA3 - Memory Controller MSA Read Data-3 Register
 ***************************************************************************/
/* MEMC_GEN_0 :: MSA_RD_DATA3 :: Data [31:00] */
#define BCHP_MEMC_GEN_0_MSA_RD_DATA3_Data_MASK                     0xffffffff
#define BCHP_MEMC_GEN_0_MSA_RD_DATA3_Data_SHIFT                    0
#define BCHP_MEMC_GEN_0_MSA_RD_DATA3_Data_DEFAULT                  0

/***************************************************************************
 *MSA_RD_DATA4 - Memory Controller MSA Read Data-4 Register
 ***************************************************************************/
/* MEMC_GEN_0 :: MSA_RD_DATA4 :: Data [31:00] */
#define BCHP_MEMC_GEN_0_MSA_RD_DATA4_Data_MASK                     0xffffffff
#define BCHP_MEMC_GEN_0_MSA_RD_DATA4_Data_SHIFT                    0
#define BCHP_MEMC_GEN_0_MSA_RD_DATA4_Data_DEFAULT                  0

/***************************************************************************
 *MSA_RD_DATA5 - Memory Controller MSA Read Data-5 Register
 ***************************************************************************/
/* MEMC_GEN_0 :: MSA_RD_DATA5 :: Data [31:00] */
#define BCHP_MEMC_GEN_0_MSA_RD_DATA5_Data_MASK                     0xffffffff
#define BCHP_MEMC_GEN_0_MSA_RD_DATA5_Data_SHIFT                    0
#define BCHP_MEMC_GEN_0_MSA_RD_DATA5_Data_DEFAULT                  0

/***************************************************************************
 *MSA_RD_DATA6 - Memory Controller MSA Read Data-6 Register
 ***************************************************************************/
/* MEMC_GEN_0 :: MSA_RD_DATA6 :: Data [31:00] */
#define BCHP_MEMC_GEN_0_MSA_RD_DATA6_Data_MASK                     0xffffffff
#define BCHP_MEMC_GEN_0_MSA_RD_DATA6_Data_SHIFT                    0
#define BCHP_MEMC_GEN_0_MSA_RD_DATA6_Data_DEFAULT                  0

/***************************************************************************
 *MSA_RD_DATA7 - Memory Controller MSA Read Data-7 Register
 ***************************************************************************/
/* MEMC_GEN_0 :: MSA_RD_DATA7 :: Data [31:00] */
#define BCHP_MEMC_GEN_0_MSA_RD_DATA7_Data_MASK                     0xffffffff
#define BCHP_MEMC_GEN_0_MSA_RD_DATA7_Data_SHIFT                    0
#define BCHP_MEMC_GEN_0_MSA_RD_DATA7_Data_DEFAULT                  0

/***************************************************************************
 *MSA_RD_DATA_CLR - MSA read data clear register.
 ***************************************************************************/
/* MEMC_GEN_0 :: MSA_RD_DATA_CLR :: reserved0 [31:01] */
#define BCHP_MEMC_GEN_0_MSA_RD_DATA_CLR_reserved0_MASK             0xfffffffe
#define BCHP_MEMC_GEN_0_MSA_RD_DATA_CLR_reserved0_SHIFT            1

/* MEMC_GEN_0 :: MSA_RD_DATA_CLR :: CLR_REGS [00:00] */
#define BCHP_MEMC_GEN_0_MSA_RD_DATA_CLR_CLR_REGS_MASK              0x00000001
#define BCHP_MEMC_GEN_0_MSA_RD_DATA_CLR_CLR_REGS_SHIFT             0
#define BCHP_MEMC_GEN_0_MSA_RD_DATA_CLR_CLR_REGS_DEFAULT           0

/***************************************************************************
 *SCB_CRC_UNIT0_ENABLE - Unit0 SCB read/write data CRC enable register.
 ***************************************************************************/
/* MEMC_GEN_0 :: SCB_CRC_UNIT0_ENABLE :: reserved0 [31:11] */
#define BCHP_MEMC_GEN_0_SCB_CRC_UNIT0_ENABLE_reserved0_MASK        0xfffff800
#define BCHP_MEMC_GEN_0_SCB_CRC_UNIT0_ENABLE_reserved0_SHIFT       11

/* MEMC_GEN_0 :: SCB_CRC_UNIT0_ENABLE :: CRC_CLIENT [10:04] */
#define BCHP_MEMC_GEN_0_SCB_CRC_UNIT0_ENABLE_CRC_CLIENT_MASK       0x000007f0
#define BCHP_MEMC_GEN_0_SCB_CRC_UNIT0_ENABLE_CRC_CLIENT_SHIFT      4
#define BCHP_MEMC_GEN_0_SCB_CRC_UNIT0_ENABLE_CRC_CLIENT_DEFAULT    0

/* MEMC_GEN_0 :: SCB_CRC_UNIT0_ENABLE :: reserved1 [03:03] */
#define BCHP_MEMC_GEN_0_SCB_CRC_UNIT0_ENABLE_reserved1_MASK        0x00000008
#define BCHP_MEMC_GEN_0_SCB_CRC_UNIT0_ENABLE_reserved1_SHIFT       3

/* MEMC_GEN_0 :: SCB_CRC_UNIT0_ENABLE :: CRC_CLEAR [02:02] */
#define BCHP_MEMC_GEN_0_SCB_CRC_UNIT0_ENABLE_CRC_CLEAR_MASK        0x00000004
#define BCHP_MEMC_GEN_0_SCB_CRC_UNIT0_ENABLE_CRC_CLEAR_SHIFT       2
#define BCHP_MEMC_GEN_0_SCB_CRC_UNIT0_ENABLE_CRC_CLEAR_DEFAULT     0

/* MEMC_GEN_0 :: SCB_CRC_UNIT0_ENABLE :: CRC_MODE [01:01] */
#define BCHP_MEMC_GEN_0_SCB_CRC_UNIT0_ENABLE_CRC_MODE_MASK         0x00000002
#define BCHP_MEMC_GEN_0_SCB_CRC_UNIT0_ENABLE_CRC_MODE_SHIFT        1
#define BCHP_MEMC_GEN_0_SCB_CRC_UNIT0_ENABLE_CRC_MODE_DEFAULT      0

/* MEMC_GEN_0 :: SCB_CRC_UNIT0_ENABLE :: CRC_EN [00:00] */
#define BCHP_MEMC_GEN_0_SCB_CRC_UNIT0_ENABLE_CRC_EN_MASK           0x00000001
#define BCHP_MEMC_GEN_0_SCB_CRC_UNIT0_ENABLE_CRC_EN_SHIFT          0
#define BCHP_MEMC_GEN_0_SCB_CRC_UNIT0_ENABLE_CRC_EN_DEFAULT        0

/***************************************************************************
 *SCB_CRC_UNIT0_0 - Unit0 SCB read data CRC register.
 ***************************************************************************/
/* MEMC_GEN_0 :: SCB_CRC_UNIT0_0 :: CRC [31:00] */
#define BCHP_MEMC_GEN_0_SCB_CRC_UNIT0_0_CRC_MASK                   0xffffffff
#define BCHP_MEMC_GEN_0_SCB_CRC_UNIT0_0_CRC_SHIFT                  0
#define BCHP_MEMC_GEN_0_SCB_CRC_UNIT0_0_CRC_DEFAULT                0

/***************************************************************************
 *SCB_CRC_UNIT0_1 - Unit0 SCB read data CRC register.
 ***************************************************************************/
/* MEMC_GEN_0 :: SCB_CRC_UNIT0_1 :: CRC [31:00] */
#define BCHP_MEMC_GEN_0_SCB_CRC_UNIT0_1_CRC_MASK                   0xffffffff
#define BCHP_MEMC_GEN_0_SCB_CRC_UNIT0_1_CRC_SHIFT                  0
#define BCHP_MEMC_GEN_0_SCB_CRC_UNIT0_1_CRC_DEFAULT                0

/***************************************************************************
 *SCB_CRC_UNIT0_2 - Unit0 SCB read data CRC register.
 ***************************************************************************/
/* MEMC_GEN_0 :: SCB_CRC_UNIT0_2 :: CRC [31:00] */
#define BCHP_MEMC_GEN_0_SCB_CRC_UNIT0_2_CRC_MASK                   0xffffffff
#define BCHP_MEMC_GEN_0_SCB_CRC_UNIT0_2_CRC_SHIFT                  0
#define BCHP_MEMC_GEN_0_SCB_CRC_UNIT0_2_CRC_DEFAULT                0

/***************************************************************************
 *SCB_CRC_UNIT0_3 - Unit0 SCB read data CRC register.
 ***************************************************************************/
/* MEMC_GEN_0 :: SCB_CRC_UNIT0_3 :: CRC [31:00] */
#define BCHP_MEMC_GEN_0_SCB_CRC_UNIT0_3_CRC_MASK                   0xffffffff
#define BCHP_MEMC_GEN_0_SCB_CRC_UNIT0_3_CRC_SHIFT                  0
#define BCHP_MEMC_GEN_0_SCB_CRC_UNIT0_3_CRC_DEFAULT                0

/***************************************************************************
 *SCB_CRC_UNIT0_4 - Unit0 SCB read data CRC register.
 ***************************************************************************/
/* MEMC_GEN_0 :: SCB_CRC_UNIT0_4 :: CRC [31:00] */
#define BCHP_MEMC_GEN_0_SCB_CRC_UNIT0_4_CRC_MASK                   0xffffffff
#define BCHP_MEMC_GEN_0_SCB_CRC_UNIT0_4_CRC_SHIFT                  0
#define BCHP_MEMC_GEN_0_SCB_CRC_UNIT0_4_CRC_DEFAULT                0

/***************************************************************************
 *SCB_CRC_UNIT0_5 - Unit0 SCB read data CRC register.
 ***************************************************************************/
/* MEMC_GEN_0 :: SCB_CRC_UNIT0_5 :: CRC [31:00] */
#define BCHP_MEMC_GEN_0_SCB_CRC_UNIT0_5_CRC_MASK                   0xffffffff
#define BCHP_MEMC_GEN_0_SCB_CRC_UNIT0_5_CRC_SHIFT                  0
#define BCHP_MEMC_GEN_0_SCB_CRC_UNIT0_5_CRC_DEFAULT                0

/***************************************************************************
 *SCB_CRC_UNIT0_6 - Unit0 SCB read data CRC register.
 ***************************************************************************/
/* MEMC_GEN_0 :: SCB_CRC_UNIT0_6 :: CRC [31:00] */
#define BCHP_MEMC_GEN_0_SCB_CRC_UNIT0_6_CRC_MASK                   0xffffffff
#define BCHP_MEMC_GEN_0_SCB_CRC_UNIT0_6_CRC_SHIFT                  0
#define BCHP_MEMC_GEN_0_SCB_CRC_UNIT0_6_CRC_DEFAULT                0

/***************************************************************************
 *SCB_CRC_UNIT0_7 - Unit0 SCB read data CRC register.
 ***************************************************************************/
/* MEMC_GEN_0 :: SCB_CRC_UNIT0_7 :: CRC [31:00] */
#define BCHP_MEMC_GEN_0_SCB_CRC_UNIT0_7_CRC_MASK                   0xffffffff
#define BCHP_MEMC_GEN_0_SCB_CRC_UNIT0_7_CRC_SHIFT                  0
#define BCHP_MEMC_GEN_0_SCB_CRC_UNIT0_7_CRC_DEFAULT                0

/***************************************************************************
 *SCB_CRC_UNIT0_8 - Unit0 SCB read data CRC register.
 ***************************************************************************/
/* MEMC_GEN_0 :: SCB_CRC_UNIT0_8 :: CRC [31:00] */
#define BCHP_MEMC_GEN_0_SCB_CRC_UNIT0_8_CRC_MASK                   0xffffffff
#define BCHP_MEMC_GEN_0_SCB_CRC_UNIT0_8_CRC_SHIFT                  0
#define BCHP_MEMC_GEN_0_SCB_CRC_UNIT0_8_CRC_DEFAULT                0

/***************************************************************************
 *SCB_CRC_UNIT0_9 - Unit0 SCB read data CRC register.
 ***************************************************************************/
/* MEMC_GEN_0 :: SCB_CRC_UNIT0_9 :: CRC [31:00] */
#define BCHP_MEMC_GEN_0_SCB_CRC_UNIT0_9_CRC_MASK                   0xffffffff
#define BCHP_MEMC_GEN_0_SCB_CRC_UNIT0_9_CRC_SHIFT                  0
#define BCHP_MEMC_GEN_0_SCB_CRC_UNIT0_9_CRC_DEFAULT                0

/***************************************************************************
 *SCB_CRC_UNIT0_10 - Unit0 SCB read data CRC register.
 ***************************************************************************/
/* MEMC_GEN_0 :: SCB_CRC_UNIT0_10 :: CRC [31:00] */
#define BCHP_MEMC_GEN_0_SCB_CRC_UNIT0_10_CRC_MASK                  0xffffffff
#define BCHP_MEMC_GEN_0_SCB_CRC_UNIT0_10_CRC_SHIFT                 0
#define BCHP_MEMC_GEN_0_SCB_CRC_UNIT0_10_CRC_DEFAULT               0

/***************************************************************************
 *SCB_CRC_UNIT0_11 - Unit0 SCB read data CRC register.
 ***************************************************************************/
/* MEMC_GEN_0 :: SCB_CRC_UNIT0_11 :: CRC [31:00] */
#define BCHP_MEMC_GEN_0_SCB_CRC_UNIT0_11_CRC_MASK                  0xffffffff
#define BCHP_MEMC_GEN_0_SCB_CRC_UNIT0_11_CRC_SHIFT                 0
#define BCHP_MEMC_GEN_0_SCB_CRC_UNIT0_11_CRC_DEFAULT               0

/***************************************************************************
 *SCB_CRC_UNIT0_12 - Unit0 SCB read data CRC register.
 ***************************************************************************/
/* MEMC_GEN_0 :: SCB_CRC_UNIT0_12 :: CRC [31:00] */
#define BCHP_MEMC_GEN_0_SCB_CRC_UNIT0_12_CRC_MASK                  0xffffffff
#define BCHP_MEMC_GEN_0_SCB_CRC_UNIT0_12_CRC_SHIFT                 0
#define BCHP_MEMC_GEN_0_SCB_CRC_UNIT0_12_CRC_DEFAULT               0

/***************************************************************************
 *SCB_CRC_UNIT0_13 - Unit0 SCB read data CRC register.
 ***************************************************************************/
/* MEMC_GEN_0 :: SCB_CRC_UNIT0_13 :: CRC [31:00] */
#define BCHP_MEMC_GEN_0_SCB_CRC_UNIT0_13_CRC_MASK                  0xffffffff
#define BCHP_MEMC_GEN_0_SCB_CRC_UNIT0_13_CRC_SHIFT                 0
#define BCHP_MEMC_GEN_0_SCB_CRC_UNIT0_13_CRC_DEFAULT               0

/***************************************************************************
 *SCB_CRC_UNIT0_14 - Unit0 SCB read data CRC register.
 ***************************************************************************/
/* MEMC_GEN_0 :: SCB_CRC_UNIT0_14 :: CRC [31:00] */
#define BCHP_MEMC_GEN_0_SCB_CRC_UNIT0_14_CRC_MASK                  0xffffffff
#define BCHP_MEMC_GEN_0_SCB_CRC_UNIT0_14_CRC_SHIFT                 0
#define BCHP_MEMC_GEN_0_SCB_CRC_UNIT0_14_CRC_DEFAULT               0

/***************************************************************************
 *SCB_CRC_UNIT0_15 - Unit0 SCB read data CRC register.
 ***************************************************************************/
/* MEMC_GEN_0 :: SCB_CRC_UNIT0_15 :: CRC [31:00] */
#define BCHP_MEMC_GEN_0_SCB_CRC_UNIT0_15_CRC_MASK                  0xffffffff
#define BCHP_MEMC_GEN_0_SCB_CRC_UNIT0_15_CRC_SHIFT                 0
#define BCHP_MEMC_GEN_0_SCB_CRC_UNIT0_15_CRC_DEFAULT               0

/***************************************************************************
 *SCB_CRC_UNIT1_ENABLE - Unit1 SCB read/write data CRC enable register.
 ***************************************************************************/
/* MEMC_GEN_0 :: SCB_CRC_UNIT1_ENABLE :: reserved0 [31:11] */
#define BCHP_MEMC_GEN_0_SCB_CRC_UNIT1_ENABLE_reserved0_MASK        0xfffff800
#define BCHP_MEMC_GEN_0_SCB_CRC_UNIT1_ENABLE_reserved0_SHIFT       11

/* MEMC_GEN_0 :: SCB_CRC_UNIT1_ENABLE :: CRC_CLIENT [10:04] */
#define BCHP_MEMC_GEN_0_SCB_CRC_UNIT1_ENABLE_CRC_CLIENT_MASK       0x000007f0
#define BCHP_MEMC_GEN_0_SCB_CRC_UNIT1_ENABLE_CRC_CLIENT_SHIFT      4
#define BCHP_MEMC_GEN_0_SCB_CRC_UNIT1_ENABLE_CRC_CLIENT_DEFAULT    0

/* MEMC_GEN_0 :: SCB_CRC_UNIT1_ENABLE :: reserved1 [03:03] */
#define BCHP_MEMC_GEN_0_SCB_CRC_UNIT1_ENABLE_reserved1_MASK        0x00000008
#define BCHP_MEMC_GEN_0_SCB_CRC_UNIT1_ENABLE_reserved1_SHIFT       3

/* MEMC_GEN_0 :: SCB_CRC_UNIT1_ENABLE :: CRC_CLEAR [02:02] */
#define BCHP_MEMC_GEN_0_SCB_CRC_UNIT1_ENABLE_CRC_CLEAR_MASK        0x00000004
#define BCHP_MEMC_GEN_0_SCB_CRC_UNIT1_ENABLE_CRC_CLEAR_SHIFT       2
#define BCHP_MEMC_GEN_0_SCB_CRC_UNIT1_ENABLE_CRC_CLEAR_DEFAULT     0

/* MEMC_GEN_0 :: SCB_CRC_UNIT1_ENABLE :: CRC_MODE [01:01] */
#define BCHP_MEMC_GEN_0_SCB_CRC_UNIT1_ENABLE_CRC_MODE_MASK         0x00000002
#define BCHP_MEMC_GEN_0_SCB_CRC_UNIT1_ENABLE_CRC_MODE_SHIFT        1
#define BCHP_MEMC_GEN_0_SCB_CRC_UNIT1_ENABLE_CRC_MODE_DEFAULT      0

/* MEMC_GEN_0 :: SCB_CRC_UNIT1_ENABLE :: CRC_EN [00:00] */
#define BCHP_MEMC_GEN_0_SCB_CRC_UNIT1_ENABLE_CRC_EN_MASK           0x00000001
#define BCHP_MEMC_GEN_0_SCB_CRC_UNIT1_ENABLE_CRC_EN_SHIFT          0
#define BCHP_MEMC_GEN_0_SCB_CRC_UNIT1_ENABLE_CRC_EN_DEFAULT        0

/***************************************************************************
 *SCB_CRC_UNIT1_0 - Unit1 SCB read data CRC register.
 ***************************************************************************/
/* MEMC_GEN_0 :: SCB_CRC_UNIT1_0 :: CRC [31:00] */
#define BCHP_MEMC_GEN_0_SCB_CRC_UNIT1_0_CRC_MASK                   0xffffffff
#define BCHP_MEMC_GEN_0_SCB_CRC_UNIT1_0_CRC_SHIFT                  0
#define BCHP_MEMC_GEN_0_SCB_CRC_UNIT1_0_CRC_DEFAULT                0

/***************************************************************************
 *SCB_CRC_UNIT1_1 - Unit1 SCB read data CRC register.
 ***************************************************************************/
/* MEMC_GEN_0 :: SCB_CRC_UNIT1_1 :: CRC [31:00] */
#define BCHP_MEMC_GEN_0_SCB_CRC_UNIT1_1_CRC_MASK                   0xffffffff
#define BCHP_MEMC_GEN_0_SCB_CRC_UNIT1_1_CRC_SHIFT                  0
#define BCHP_MEMC_GEN_0_SCB_CRC_UNIT1_1_CRC_DEFAULT                0

/***************************************************************************
 *SCB_CRC_UNIT1_2 - Unit1 SCB read data CRC register.
 ***************************************************************************/
/* MEMC_GEN_0 :: SCB_CRC_UNIT1_2 :: CRC [31:00] */
#define BCHP_MEMC_GEN_0_SCB_CRC_UNIT1_2_CRC_MASK                   0xffffffff
#define BCHP_MEMC_GEN_0_SCB_CRC_UNIT1_2_CRC_SHIFT                  0
#define BCHP_MEMC_GEN_0_SCB_CRC_UNIT1_2_CRC_DEFAULT                0

/***************************************************************************
 *SCB_CRC_UNIT1_3 - Unit1 SCB read data CRC register.
 ***************************************************************************/
/* MEMC_GEN_0 :: SCB_CRC_UNIT1_3 :: CRC [31:00] */
#define BCHP_MEMC_GEN_0_SCB_CRC_UNIT1_3_CRC_MASK                   0xffffffff
#define BCHP_MEMC_GEN_0_SCB_CRC_UNIT1_3_CRC_SHIFT                  0
#define BCHP_MEMC_GEN_0_SCB_CRC_UNIT1_3_CRC_DEFAULT                0

/***************************************************************************
 *SCB_CRC_UNIT1_4 - Unit1 SCB read data CRC register.
 ***************************************************************************/
/* MEMC_GEN_0 :: SCB_CRC_UNIT1_4 :: CRC [31:00] */
#define BCHP_MEMC_GEN_0_SCB_CRC_UNIT1_4_CRC_MASK                   0xffffffff
#define BCHP_MEMC_GEN_0_SCB_CRC_UNIT1_4_CRC_SHIFT                  0
#define BCHP_MEMC_GEN_0_SCB_CRC_UNIT1_4_CRC_DEFAULT                0

/***************************************************************************
 *SCB_CRC_UNIT1_5 - Unit1 SCB read data CRC register.
 ***************************************************************************/
/* MEMC_GEN_0 :: SCB_CRC_UNIT1_5 :: CRC [31:00] */
#define BCHP_MEMC_GEN_0_SCB_CRC_UNIT1_5_CRC_MASK                   0xffffffff
#define BCHP_MEMC_GEN_0_SCB_CRC_UNIT1_5_CRC_SHIFT                  0
#define BCHP_MEMC_GEN_0_SCB_CRC_UNIT1_5_CRC_DEFAULT                0

/***************************************************************************
 *SCB_CRC_UNIT1_6 - Unit1 SCB read data CRC register.
 ***************************************************************************/
/* MEMC_GEN_0 :: SCB_CRC_UNIT1_6 :: CRC [31:00] */
#define BCHP_MEMC_GEN_0_SCB_CRC_UNIT1_6_CRC_MASK                   0xffffffff
#define BCHP_MEMC_GEN_0_SCB_CRC_UNIT1_6_CRC_SHIFT                  0
#define BCHP_MEMC_GEN_0_SCB_CRC_UNIT1_6_CRC_DEFAULT                0

/***************************************************************************
 *SCB_CRC_UNIT1_7 - Unit1 SCB read data CRC register.
 ***************************************************************************/
/* MEMC_GEN_0 :: SCB_CRC_UNIT1_7 :: CRC [31:00] */
#define BCHP_MEMC_GEN_0_SCB_CRC_UNIT1_7_CRC_MASK                   0xffffffff
#define BCHP_MEMC_GEN_0_SCB_CRC_UNIT1_7_CRC_SHIFT                  0
#define BCHP_MEMC_GEN_0_SCB_CRC_UNIT1_7_CRC_DEFAULT                0

/***************************************************************************
 *SCB_CRC_UNIT1_8 - Unit1 SCB read data CRC register.
 ***************************************************************************/
/* MEMC_GEN_0 :: SCB_CRC_UNIT1_8 :: CRC [31:00] */
#define BCHP_MEMC_GEN_0_SCB_CRC_UNIT1_8_CRC_MASK                   0xffffffff
#define BCHP_MEMC_GEN_0_SCB_CRC_UNIT1_8_CRC_SHIFT                  0
#define BCHP_MEMC_GEN_0_SCB_CRC_UNIT1_8_CRC_DEFAULT                0

/***************************************************************************
 *SCB_CRC_UNIT1_9 - Unit1 SCB read data CRC register.
 ***************************************************************************/
/* MEMC_GEN_0 :: SCB_CRC_UNIT1_9 :: CRC [31:00] */
#define BCHP_MEMC_GEN_0_SCB_CRC_UNIT1_9_CRC_MASK                   0xffffffff
#define BCHP_MEMC_GEN_0_SCB_CRC_UNIT1_9_CRC_SHIFT                  0
#define BCHP_MEMC_GEN_0_SCB_CRC_UNIT1_9_CRC_DEFAULT                0

/***************************************************************************
 *SCB_CRC_UNIT1_10 - Unit1 SCB read data CRC register.
 ***************************************************************************/
/* MEMC_GEN_0 :: SCB_CRC_UNIT1_10 :: CRC [31:00] */
#define BCHP_MEMC_GEN_0_SCB_CRC_UNIT1_10_CRC_MASK                  0xffffffff
#define BCHP_MEMC_GEN_0_SCB_CRC_UNIT1_10_CRC_SHIFT                 0
#define BCHP_MEMC_GEN_0_SCB_CRC_UNIT1_10_CRC_DEFAULT               0

/***************************************************************************
 *SCB_CRC_UNIT1_11 - Unit1 SCB read data CRC register.
 ***************************************************************************/
/* MEMC_GEN_0 :: SCB_CRC_UNIT1_11 :: CRC [31:00] */
#define BCHP_MEMC_GEN_0_SCB_CRC_UNIT1_11_CRC_MASK                  0xffffffff
#define BCHP_MEMC_GEN_0_SCB_CRC_UNIT1_11_CRC_SHIFT                 0
#define BCHP_MEMC_GEN_0_SCB_CRC_UNIT1_11_CRC_DEFAULT               0

/***************************************************************************
 *SCB_CRC_UNIT1_12 - Unit1 SCB read data CRC register.
 ***************************************************************************/
/* MEMC_GEN_0 :: SCB_CRC_UNIT1_12 :: CRC [31:00] */
#define BCHP_MEMC_GEN_0_SCB_CRC_UNIT1_12_CRC_MASK                  0xffffffff
#define BCHP_MEMC_GEN_0_SCB_CRC_UNIT1_12_CRC_SHIFT                 0
#define BCHP_MEMC_GEN_0_SCB_CRC_UNIT1_12_CRC_DEFAULT               0

/***************************************************************************
 *SCB_CRC_UNIT1_13 - Unit1 SCB read data CRC register.
 ***************************************************************************/
/* MEMC_GEN_0 :: SCB_CRC_UNIT1_13 :: CRC [31:00] */
#define BCHP_MEMC_GEN_0_SCB_CRC_UNIT1_13_CRC_MASK                  0xffffffff
#define BCHP_MEMC_GEN_0_SCB_CRC_UNIT1_13_CRC_SHIFT                 0
#define BCHP_MEMC_GEN_0_SCB_CRC_UNIT1_13_CRC_DEFAULT               0

/***************************************************************************
 *SCB_CRC_UNIT1_14 - Unit1 SCB read data CRC register.
 ***************************************************************************/
/* MEMC_GEN_0 :: SCB_CRC_UNIT1_14 :: CRC [31:00] */
#define BCHP_MEMC_GEN_0_SCB_CRC_UNIT1_14_CRC_MASK                  0xffffffff
#define BCHP_MEMC_GEN_0_SCB_CRC_UNIT1_14_CRC_SHIFT                 0
#define BCHP_MEMC_GEN_0_SCB_CRC_UNIT1_14_CRC_DEFAULT               0

/***************************************************************************
 *SCB_CRC_UNIT1_15 - Unit1 SCB read data CRC register.
 ***************************************************************************/
/* MEMC_GEN_0 :: SCB_CRC_UNIT1_15 :: CRC [31:00] */
#define BCHP_MEMC_GEN_0_SCB_CRC_UNIT1_15_CRC_MASK                  0xffffffff
#define BCHP_MEMC_GEN_0_SCB_CRC_UNIT1_15_CRC_SHIFT                 0
#define BCHP_MEMC_GEN_0_SCB_CRC_UNIT1_15_CRC_DEFAULT               0

/***************************************************************************
 *DIS_CLIENT0_CMD - DDR interface stress client 0 command register.
 ***************************************************************************/
/* MEMC_GEN_0 :: DIS_CLIENT0_CMD :: reserved0 [31:26] */
#define BCHP_MEMC_GEN_0_DIS_CLIENT0_CMD_reserved0_MASK             0xfc000000
#define BCHP_MEMC_GEN_0_DIS_CLIENT0_CMD_reserved0_SHIFT            26

/* MEMC_GEN_0 :: DIS_CLIENT0_CMD :: BYPASS_PADS [25:25] */
#define BCHP_MEMC_GEN_0_DIS_CLIENT0_CMD_BYPASS_PADS_MASK           0x02000000
#define BCHP_MEMC_GEN_0_DIS_CLIENT0_CMD_BYPASS_PADS_SHIFT          25
#define BCHP_MEMC_GEN_0_DIS_CLIENT0_CMD_BYPASS_PADS_DEFAULT        1
#define BCHP_MEMC_GEN_0_DIS_CLIENT0_CMD_BYPASS_PADS_YES            1
#define BCHP_MEMC_GEN_0_DIS_CLIENT0_CMD_BYPASS_PADS_NO             0

/* MEMC_GEN_0 :: DIS_CLIENT0_CMD :: MODE [24:23] */
#define BCHP_MEMC_GEN_0_DIS_CLIENT0_CMD_MODE_MASK                  0x01800000
#define BCHP_MEMC_GEN_0_DIS_CLIENT0_CMD_MODE_SHIFT                 23
#define BCHP_MEMC_GEN_0_DIS_CLIENT0_CMD_MODE_DEFAULT               0

/* MEMC_GEN_0 :: DIS_CLIENT0_CMD :: DATA_PATTERN [22:21] */
#define BCHP_MEMC_GEN_0_DIS_CLIENT0_CMD_DATA_PATTERN_MASK          0x00600000
#define BCHP_MEMC_GEN_0_DIS_CLIENT0_CMD_DATA_PATTERN_SHIFT         21
#define BCHP_MEMC_GEN_0_DIS_CLIENT0_CMD_DATA_PATTERN_DEFAULT       0

/* MEMC_GEN_0 :: DIS_CLIENT0_CMD :: BURST_LEN [20:16] */
#define BCHP_MEMC_GEN_0_DIS_CLIENT0_CMD_BURST_LEN_MASK             0x001f0000
#define BCHP_MEMC_GEN_0_DIS_CLIENT0_CMD_BURST_LEN_SHIFT            16
#define BCHP_MEMC_GEN_0_DIS_CLIENT0_CMD_BURST_LEN_DEFAULT          0

/* MEMC_GEN_0 :: DIS_CLIENT0_CMD :: STEP_SIZE [15:00] */
#define BCHP_MEMC_GEN_0_DIS_CLIENT0_CMD_STEP_SIZE_MASK             0x0000ffff
#define BCHP_MEMC_GEN_0_DIS_CLIENT0_CMD_STEP_SIZE_SHIFT            0
#define BCHP_MEMC_GEN_0_DIS_CLIENT0_CMD_STEP_SIZE_DEFAULT          0

/***************************************************************************
 *DIS_CLIENT0_START_ADDR - DDR interface stress client 0 start address register.
 ***************************************************************************/
/* MEMC_GEN_0 :: DIS_CLIENT0_START_ADDR :: reserved0 [31:29] */
#define BCHP_MEMC_GEN_0_DIS_CLIENT0_START_ADDR_reserved0_MASK      0xe0000000
#define BCHP_MEMC_GEN_0_DIS_CLIENT0_START_ADDR_reserved0_SHIFT     29

/* MEMC_GEN_0 :: DIS_CLIENT0_START_ADDR :: START_ADDR [28:00] */
#define BCHP_MEMC_GEN_0_DIS_CLIENT0_START_ADDR_START_ADDR_MASK     0x1fffffff
#define BCHP_MEMC_GEN_0_DIS_CLIENT0_START_ADDR_START_ADDR_SHIFT    0
#define BCHP_MEMC_GEN_0_DIS_CLIENT0_START_ADDR_START_ADDR_DEFAULT  0

/***************************************************************************
 *DIS_CLIENT0_END_ADDR - DDR interface stress client 0 end address register.
 ***************************************************************************/
/* MEMC_GEN_0 :: DIS_CLIENT0_END_ADDR :: reserved0 [31:31] */
#define BCHP_MEMC_GEN_0_DIS_CLIENT0_END_ADDR_reserved0_MASK        0x80000000
#define BCHP_MEMC_GEN_0_DIS_CLIENT0_END_ADDR_reserved0_SHIFT       31

/* MEMC_GEN_0 :: DIS_CLIENT0_END_ADDR :: LOOP_MODE [30:30] */
#define BCHP_MEMC_GEN_0_DIS_CLIENT0_END_ADDR_LOOP_MODE_MASK        0x40000000
#define BCHP_MEMC_GEN_0_DIS_CLIENT0_END_ADDR_LOOP_MODE_SHIFT       30
#define BCHP_MEMC_GEN_0_DIS_CLIENT0_END_ADDR_LOOP_MODE_DEFAULT     0

/* MEMC_GEN_0 :: DIS_CLIENT0_END_ADDR :: DISABLE_TIMEOUT [29:29] */
#define BCHP_MEMC_GEN_0_DIS_CLIENT0_END_ADDR_DISABLE_TIMEOUT_MASK  0x20000000
#define BCHP_MEMC_GEN_0_DIS_CLIENT0_END_ADDR_DISABLE_TIMEOUT_SHIFT 29
#define BCHP_MEMC_GEN_0_DIS_CLIENT0_END_ADDR_DISABLE_TIMEOUT_DEFAULT 0

/* MEMC_GEN_0 :: DIS_CLIENT0_END_ADDR :: END_ADDR [28:00] */
#define BCHP_MEMC_GEN_0_DIS_CLIENT0_END_ADDR_END_ADDR_MASK         0x1fffffff
#define BCHP_MEMC_GEN_0_DIS_CLIENT0_END_ADDR_END_ADDR_SHIFT        0
#define BCHP_MEMC_GEN_0_DIS_CLIENT0_END_ADDR_END_ADDR_DEFAULT      0

/***************************************************************************
 *DIS_CLIENT0_DQM - DDR interface stress client 0 DQM Register
 ***************************************************************************/
/* MEMC_GEN_0 :: DIS_CLIENT0_DQM :: DQM [31:00] */
#define BCHP_MEMC_GEN_0_DIS_CLIENT0_DQM_DQM_MASK                   0xffffffff
#define BCHP_MEMC_GEN_0_DIS_CLIENT0_DQM_DQM_SHIFT                  0
#define BCHP_MEMC_GEN_0_DIS_CLIENT0_DQM_DQM_DEFAULT                0

/***************************************************************************
 *DIS_CLIENT0_TRIGGER - DDR interface stress client 0 start register.
 ***************************************************************************/
/* MEMC_GEN_0 :: DIS_CLIENT0_TRIGGER :: reserved0 [31:01] */
#define BCHP_MEMC_GEN_0_DIS_CLIENT0_TRIGGER_reserved0_MASK         0xfffffffe
#define BCHP_MEMC_GEN_0_DIS_CLIENT0_TRIGGER_reserved0_SHIFT        1

/* MEMC_GEN_0 :: DIS_CLIENT0_TRIGGER :: START_TEST [00:00] */
#define BCHP_MEMC_GEN_0_DIS_CLIENT0_TRIGGER_START_TEST_MASK        0x00000001
#define BCHP_MEMC_GEN_0_DIS_CLIENT0_TRIGGER_START_TEST_SHIFT       0
#define BCHP_MEMC_GEN_0_DIS_CLIENT0_TRIGGER_START_TEST_DEFAULT     0

/***************************************************************************
 *DIS_CLIENT0_STATUS - DDR interface stress client 0 status register.
 ***************************************************************************/
/* MEMC_GEN_0 :: DIS_CLIENT0_STATUS :: reserved0 [31:11] */
#define BCHP_MEMC_GEN_0_DIS_CLIENT0_STATUS_reserved0_MASK          0xfffff800
#define BCHP_MEMC_GEN_0_DIS_CLIENT0_STATUS_reserved0_SHIFT         11

/* MEMC_GEN_0 :: DIS_CLIENT0_STATUS :: TIMEOUT_OCCURED [10:10] */
#define BCHP_MEMC_GEN_0_DIS_CLIENT0_STATUS_TIMEOUT_OCCURED_MASK    0x00000400
#define BCHP_MEMC_GEN_0_DIS_CLIENT0_STATUS_TIMEOUT_OCCURED_SHIFT   10
#define BCHP_MEMC_GEN_0_DIS_CLIENT0_STATUS_TIMEOUT_OCCURED_DEFAULT 0

/* MEMC_GEN_0 :: DIS_CLIENT0_STATUS :: CURRENT_STATE [09:08] */
#define BCHP_MEMC_GEN_0_DIS_CLIENT0_STATUS_CURRENT_STATE_MASK      0x00000300
#define BCHP_MEMC_GEN_0_DIS_CLIENT0_STATUS_CURRENT_STATE_SHIFT     8
#define BCHP_MEMC_GEN_0_DIS_CLIENT0_STATUS_CURRENT_STATE_DEFAULT   0

/* MEMC_GEN_0 :: DIS_CLIENT0_STATUS :: DQM_MATCH [07:04] */
#define BCHP_MEMC_GEN_0_DIS_CLIENT0_STATUS_DQM_MATCH_MASK          0x000000f0
#define BCHP_MEMC_GEN_0_DIS_CLIENT0_STATUS_DQM_MATCH_SHIFT         4
#define BCHP_MEMC_GEN_0_DIS_CLIENT0_STATUS_DQM_MATCH_DEFAULT       0

/* MEMC_GEN_0 :: DIS_CLIENT0_STATUS :: ADDR_CTRL_MATCH_SET1 [03:03] */
#define BCHP_MEMC_GEN_0_DIS_CLIENT0_STATUS_ADDR_CTRL_MATCH_SET1_MASK 0x00000008
#define BCHP_MEMC_GEN_0_DIS_CLIENT0_STATUS_ADDR_CTRL_MATCH_SET1_SHIFT 3
#define BCHP_MEMC_GEN_0_DIS_CLIENT0_STATUS_ADDR_CTRL_MATCH_SET1_DEFAULT 0
#define BCHP_MEMC_GEN_0_DIS_CLIENT0_STATUS_ADDR_CTRL_MATCH_SET1_YES 1
#define BCHP_MEMC_GEN_0_DIS_CLIENT0_STATUS_ADDR_CTRL_MATCH_SET1_NO 0

/* MEMC_GEN_0 :: DIS_CLIENT0_STATUS :: ADDR_CTRL_MATCH_SET0 [02:02] */
#define BCHP_MEMC_GEN_0_DIS_CLIENT0_STATUS_ADDR_CTRL_MATCH_SET0_MASK 0x00000004
#define BCHP_MEMC_GEN_0_DIS_CLIENT0_STATUS_ADDR_CTRL_MATCH_SET0_SHIFT 2
#define BCHP_MEMC_GEN_0_DIS_CLIENT0_STATUS_ADDR_CTRL_MATCH_SET0_DEFAULT 0
#define BCHP_MEMC_GEN_0_DIS_CLIENT0_STATUS_ADDR_CTRL_MATCH_SET0_YES 1
#define BCHP_MEMC_GEN_0_DIS_CLIENT0_STATUS_ADDR_CTRL_MATCH_SET0_NO 0

/* MEMC_GEN_0 :: DIS_CLIENT0_STATUS :: LBIST_TEST_PASSED [01:01] */
#define BCHP_MEMC_GEN_0_DIS_CLIENT0_STATUS_LBIST_TEST_PASSED_MASK  0x00000002
#define BCHP_MEMC_GEN_0_DIS_CLIENT0_STATUS_LBIST_TEST_PASSED_SHIFT 1
#define BCHP_MEMC_GEN_0_DIS_CLIENT0_STATUS_LBIST_TEST_PASSED_DEFAULT 0
#define BCHP_MEMC_GEN_0_DIS_CLIENT0_STATUS_LBIST_TEST_PASSED_YES   1
#define BCHP_MEMC_GEN_0_DIS_CLIENT0_STATUS_LBIST_TEST_PASSED_NO    0

/* MEMC_GEN_0 :: DIS_CLIENT0_STATUS :: TEST_DONE [00:00] */
#define BCHP_MEMC_GEN_0_DIS_CLIENT0_STATUS_TEST_DONE_MASK          0x00000001
#define BCHP_MEMC_GEN_0_DIS_CLIENT0_STATUS_TEST_DONE_SHIFT         0
#define BCHP_MEMC_GEN_0_DIS_CLIENT0_STATUS_TEST_DONE_DEFAULT       0
#define BCHP_MEMC_GEN_0_DIS_CLIENT0_STATUS_TEST_DONE_YES           1
#define BCHP_MEMC_GEN_0_DIS_CLIENT0_STATUS_TEST_DONE_NO            0

/***************************************************************************
 *DIS_CLIENT0_STATUS_1 - DDR interface stress client 0 status register.
 ***************************************************************************/
/* MEMC_GEN_0 :: DIS_CLIENT0_STATUS_1 :: DATA_CRC_MATCH [31:00] */
#define BCHP_MEMC_GEN_0_DIS_CLIENT0_STATUS_1_DATA_CRC_MATCH_MASK   0xffffffff
#define BCHP_MEMC_GEN_0_DIS_CLIENT0_STATUS_1_DATA_CRC_MATCH_SHIFT  0
#define BCHP_MEMC_GEN_0_DIS_CLIENT0_STATUS_1_DATA_CRC_MATCH_DEFAULT 0

/***************************************************************************
 *DIS_CLIENT0_STATUS_2 - DDR interface stress client 0 status register.
 ***************************************************************************/
/* MEMC_GEN_0 :: DIS_CLIENT0_STATUS_2 :: WRITE_JWORD_COUNT [31:00] */
#define BCHP_MEMC_GEN_0_DIS_CLIENT0_STATUS_2_WRITE_JWORD_COUNT_MASK 0xffffffff
#define BCHP_MEMC_GEN_0_DIS_CLIENT0_STATUS_2_WRITE_JWORD_COUNT_SHIFT 0
#define BCHP_MEMC_GEN_0_DIS_CLIENT0_STATUS_2_WRITE_JWORD_COUNT_DEFAULT 0

/***************************************************************************
 *DIS_CLIENT0_STATUS_3 - DDR interface stress client 0 status register.
 ***************************************************************************/
/* MEMC_GEN_0 :: DIS_CLIENT0_STATUS_3 :: READ_JWORD_COUNT [31:00] */
#define BCHP_MEMC_GEN_0_DIS_CLIENT0_STATUS_3_READ_JWORD_COUNT_MASK 0xffffffff
#define BCHP_MEMC_GEN_0_DIS_CLIENT0_STATUS_3_READ_JWORD_COUNT_SHIFT 0
#define BCHP_MEMC_GEN_0_DIS_CLIENT0_STATUS_3_READ_JWORD_COUNT_DEFAULT 0

/***************************************************************************
 *SM_TIMEOUT_INTR_INFO - MEMC State Machine Timeout Interrupt Information
 ***************************************************************************/
/* MEMC_GEN_0 :: SM_TIMEOUT_INTR_INFO :: reserved0 [31:08] */
#define BCHP_MEMC_GEN_0_SM_TIMEOUT_INTR_INFO_reserved0_MASK        0xffffff00
#define BCHP_MEMC_GEN_0_SM_TIMEOUT_INTR_INFO_reserved0_SHIFT       8

/* MEMC_GEN_0 :: SM_TIMEOUT_INTR_INFO :: STATE [07:00] */
#define BCHP_MEMC_GEN_0_SM_TIMEOUT_INTR_INFO_STATE_MASK            0x000000ff
#define BCHP_MEMC_GEN_0_SM_TIMEOUT_INTR_INFO_STATE_SHIFT           0
#define BCHP_MEMC_GEN_0_SM_TIMEOUT_INTR_INFO_STATE_DEFAULT         0

/***************************************************************************
 *SM_TIMEOUT_INTR_WRITE_CLEAR - MEMC State Machine timeout interrupt write clear register
 ***************************************************************************/
/* MEMC_GEN_0 :: SM_TIMEOUT_INTR_WRITE_CLEAR :: reserved0 [31:01] */
#define BCHP_MEMC_GEN_0_SM_TIMEOUT_INTR_WRITE_CLEAR_reserved0_MASK 0xfffffffe
#define BCHP_MEMC_GEN_0_SM_TIMEOUT_INTR_WRITE_CLEAR_reserved0_SHIFT 1

/* MEMC_GEN_0 :: SM_TIMEOUT_INTR_WRITE_CLEAR :: WRITE_CLEAR [00:00] */
#define BCHP_MEMC_GEN_0_SM_TIMEOUT_INTR_WRITE_CLEAR_WRITE_CLEAR_MASK 0x00000001
#define BCHP_MEMC_GEN_0_SM_TIMEOUT_INTR_WRITE_CLEAR_WRITE_CLEAR_SHIFT 0
#define BCHP_MEMC_GEN_0_SM_TIMEOUT_INTR_WRITE_CLEAR_WRITE_CLEAR_DEFAULT 0

/***************************************************************************
 *SCB_NOREQ_INTR_INFO - MEMC Premature Request Withdrawal Interrupt Information
 ***************************************************************************/
/* MEMC_GEN_0 :: SCB_NOREQ_INTR_INFO :: reserved0 [31:07] */
#define BCHP_MEMC_GEN_0_SCB_NOREQ_INTR_INFO_reserved0_MASK         0xffffff80
#define BCHP_MEMC_GEN_0_SCB_NOREQ_INTR_INFO_reserved0_SHIFT        7

/* MEMC_GEN_0 :: SCB_NOREQ_INTR_INFO :: CLIENTID [06:00] */
#define BCHP_MEMC_GEN_0_SCB_NOREQ_INTR_INFO_CLIENTID_MASK          0x0000007f
#define BCHP_MEMC_GEN_0_SCB_NOREQ_INTR_INFO_CLIENTID_SHIFT         0
#define BCHP_MEMC_GEN_0_SCB_NOREQ_INTR_INFO_CLIENTID_DEFAULT       0

/***************************************************************************
 *SCB_NOREQ_INTR_WRITE_CLEAR - MEMC No Request interrupt write clear register
 ***************************************************************************/
/* MEMC_GEN_0 :: SCB_NOREQ_INTR_WRITE_CLEAR :: reserved0 [31:01] */
#define BCHP_MEMC_GEN_0_SCB_NOREQ_INTR_WRITE_CLEAR_reserved0_MASK  0xfffffffe
#define BCHP_MEMC_GEN_0_SCB_NOREQ_INTR_WRITE_CLEAR_reserved0_SHIFT 1

/* MEMC_GEN_0 :: SCB_NOREQ_INTR_WRITE_CLEAR :: WRITE_CLEAR [00:00] */
#define BCHP_MEMC_GEN_0_SCB_NOREQ_INTR_WRITE_CLEAR_WRITE_CLEAR_MASK 0x00000001
#define BCHP_MEMC_GEN_0_SCB_NOREQ_INTR_WRITE_CLEAR_WRITE_CLEAR_SHIFT 0
#define BCHP_MEMC_GEN_0_SCB_NOREQ_INTR_WRITE_CLEAR_WRITE_CLEAR_DEFAULT 0

/***************************************************************************
 *SCB_CMD_INTR_INFO - MEMC Illegal Command Interrupt Information
 ***************************************************************************/
/* MEMC_GEN_0 :: SCB_CMD_INTR_INFO :: reserved0 [31:25] */
#define BCHP_MEMC_GEN_0_SCB_CMD_INTR_INFO_reserved0_MASK           0xfe000000
#define BCHP_MEMC_GEN_0_SCB_CMD_INTR_INFO_reserved0_SHIFT          25

/* MEMC_GEN_0 :: SCB_CMD_INTR_INFO :: REQ_TYPE [24:16] */
#define BCHP_MEMC_GEN_0_SCB_CMD_INTR_INFO_REQ_TYPE_MASK            0x01ff0000
#define BCHP_MEMC_GEN_0_SCB_CMD_INTR_INFO_REQ_TYPE_SHIFT           16
#define BCHP_MEMC_GEN_0_SCB_CMD_INTR_INFO_REQ_TYPE_DEFAULT         0

/* MEMC_GEN_0 :: SCB_CMD_INTR_INFO :: reserved1 [15:07] */
#define BCHP_MEMC_GEN_0_SCB_CMD_INTR_INFO_reserved1_MASK           0x0000ff80
#define BCHP_MEMC_GEN_0_SCB_CMD_INTR_INFO_reserved1_SHIFT          7

/* MEMC_GEN_0 :: SCB_CMD_INTR_INFO :: CLIENTID [06:00] */
#define BCHP_MEMC_GEN_0_SCB_CMD_INTR_INFO_CLIENTID_MASK            0x0000007f
#define BCHP_MEMC_GEN_0_SCB_CMD_INTR_INFO_CLIENTID_SHIFT           0
#define BCHP_MEMC_GEN_0_SCB_CMD_INTR_INFO_CLIENTID_DEFAULT         0

/***************************************************************************
 *SCB_CMD_INTR_WRITE_CLEAR - MEMC Command interrupt write clear register
 ***************************************************************************/
/* MEMC_GEN_0 :: SCB_CMD_INTR_WRITE_CLEAR :: reserved0 [31:01] */
#define BCHP_MEMC_GEN_0_SCB_CMD_INTR_WRITE_CLEAR_reserved0_MASK    0xfffffffe
#define BCHP_MEMC_GEN_0_SCB_CMD_INTR_WRITE_CLEAR_reserved0_SHIFT   1

/* MEMC_GEN_0 :: SCB_CMD_INTR_WRITE_CLEAR :: WRITE_CLEAR [00:00] */
#define BCHP_MEMC_GEN_0_SCB_CMD_INTR_WRITE_CLEAR_WRITE_CLEAR_MASK  0x00000001
#define BCHP_MEMC_GEN_0_SCB_CMD_INTR_WRITE_CLEAR_WRITE_CLEAR_SHIFT 0
#define BCHP_MEMC_GEN_0_SCB_CMD_INTR_WRITE_CLEAR_WRITE_CLEAR_DEFAULT 0

/***************************************************************************
 *SCB_NMB_INTR_INFO - MEMC Illegal NMB Interrupt Information
 ***************************************************************************/
/* MEMC_GEN_0 :: SCB_NMB_INTR_INFO :: reserved0 [31:31] */
#define BCHP_MEMC_GEN_0_SCB_NMB_INTR_INFO_reserved0_MASK           0x80000000
#define BCHP_MEMC_GEN_0_SCB_NMB_INTR_INFO_reserved0_SHIFT          31

/* MEMC_GEN_0 :: SCB_NMB_INTR_INFO :: CLIENTID [30:24] */
#define BCHP_MEMC_GEN_0_SCB_NMB_INTR_INFO_CLIENTID_MASK            0x7f000000
#define BCHP_MEMC_GEN_0_SCB_NMB_INTR_INFO_CLIENTID_SHIFT           24
#define BCHP_MEMC_GEN_0_SCB_NMB_INTR_INFO_CLIENTID_DEFAULT         0

/* MEMC_GEN_0 :: SCB_NMB_INTR_INFO :: reserved1 [23:22] */
#define BCHP_MEMC_GEN_0_SCB_NMB_INTR_INFO_reserved1_MASK           0x00c00000
#define BCHP_MEMC_GEN_0_SCB_NMB_INTR_INFO_reserved1_SHIFT          22

/* MEMC_GEN_0 :: SCB_NMB_INTR_INFO :: NMB [21:12] */
#define BCHP_MEMC_GEN_0_SCB_NMB_INTR_INFO_NMB_MASK                 0x003ff000
#define BCHP_MEMC_GEN_0_SCB_NMB_INTR_INFO_NMB_SHIFT                12
#define BCHP_MEMC_GEN_0_SCB_NMB_INTR_INFO_NMB_DEFAULT              0

/* MEMC_GEN_0 :: SCB_NMB_INTR_INFO :: reserved2 [11:09] */
#define BCHP_MEMC_GEN_0_SCB_NMB_INTR_INFO_reserved2_MASK           0x00000e00
#define BCHP_MEMC_GEN_0_SCB_NMB_INTR_INFO_reserved2_SHIFT          9

/* MEMC_GEN_0 :: SCB_NMB_INTR_INFO :: REQ_TYPE [08:00] */
#define BCHP_MEMC_GEN_0_SCB_NMB_INTR_INFO_REQ_TYPE_MASK            0x000001ff
#define BCHP_MEMC_GEN_0_SCB_NMB_INTR_INFO_REQ_TYPE_SHIFT           0
#define BCHP_MEMC_GEN_0_SCB_NMB_INTR_INFO_REQ_TYPE_DEFAULT         0

/***************************************************************************
 *SCB_NMB_INTR_WRITE_CLEAR - MEMC Illegal NMB interrupt write clear register
 ***************************************************************************/
/* MEMC_GEN_0 :: SCB_NMB_INTR_WRITE_CLEAR :: reserved0 [31:01] */
#define BCHP_MEMC_GEN_0_SCB_NMB_INTR_WRITE_CLEAR_reserved0_MASK    0xfffffffe
#define BCHP_MEMC_GEN_0_SCB_NMB_INTR_WRITE_CLEAR_reserved0_SHIFT   1

/* MEMC_GEN_0 :: SCB_NMB_INTR_WRITE_CLEAR :: WRITE_CLEAR [00:00] */
#define BCHP_MEMC_GEN_0_SCB_NMB_INTR_WRITE_CLEAR_WRITE_CLEAR_MASK  0x00000001
#define BCHP_MEMC_GEN_0_SCB_NMB_INTR_WRITE_CLEAR_WRITE_CLEAR_SHIFT 0
#define BCHP_MEMC_GEN_0_SCB_NMB_INTR_WRITE_CLEAR_WRITE_CLEAR_DEFAULT 0

/***************************************************************************
 *SCB_START_ADDR_INTR_INFO - MEMC Illegal Start Address Interrupt Information
 ***************************************************************************/
/* MEMC_GEN_0 :: SCB_START_ADDR_INTR_INFO :: reserved0 [31:25] */
#define BCHP_MEMC_GEN_0_SCB_START_ADDR_INTR_INFO_reserved0_MASK    0xfe000000
#define BCHP_MEMC_GEN_0_SCB_START_ADDR_INTR_INFO_reserved0_SHIFT   25

/* MEMC_GEN_0 :: SCB_START_ADDR_INTR_INFO :: REQ_TYPE [24:16] */
#define BCHP_MEMC_GEN_0_SCB_START_ADDR_INTR_INFO_REQ_TYPE_MASK     0x01ff0000
#define BCHP_MEMC_GEN_0_SCB_START_ADDR_INTR_INFO_REQ_TYPE_SHIFT    16
#define BCHP_MEMC_GEN_0_SCB_START_ADDR_INTR_INFO_REQ_TYPE_DEFAULT  0

/* MEMC_GEN_0 :: SCB_START_ADDR_INTR_INFO :: reserved1 [15:13] */
#define BCHP_MEMC_GEN_0_SCB_START_ADDR_INTR_INFO_reserved1_MASK    0x0000e000
#define BCHP_MEMC_GEN_0_SCB_START_ADDR_INTR_INFO_reserved1_SHIFT   13

/* MEMC_GEN_0 :: SCB_START_ADDR_INTR_INFO :: ADDR [12:08] */
#define BCHP_MEMC_GEN_0_SCB_START_ADDR_INTR_INFO_ADDR_MASK         0x00001f00
#define BCHP_MEMC_GEN_0_SCB_START_ADDR_INTR_INFO_ADDR_SHIFT        8
#define BCHP_MEMC_GEN_0_SCB_START_ADDR_INTR_INFO_ADDR_DEFAULT      0

/* MEMC_GEN_0 :: SCB_START_ADDR_INTR_INFO :: reserved2 [07:07] */
#define BCHP_MEMC_GEN_0_SCB_START_ADDR_INTR_INFO_reserved2_MASK    0x00000080
#define BCHP_MEMC_GEN_0_SCB_START_ADDR_INTR_INFO_reserved2_SHIFT   7

/* MEMC_GEN_0 :: SCB_START_ADDR_INTR_INFO :: CLIENTID [06:00] */
#define BCHP_MEMC_GEN_0_SCB_START_ADDR_INTR_INFO_CLIENTID_MASK     0x0000007f
#define BCHP_MEMC_GEN_0_SCB_START_ADDR_INTR_INFO_CLIENTID_SHIFT    0
#define BCHP_MEMC_GEN_0_SCB_START_ADDR_INTR_INFO_CLIENTID_DEFAULT  0

/***************************************************************************
 *SCB_START_ADDR_INTR_WRITE_CLEAR - MEMC Illegal Start Addr interrupt write clear register
 ***************************************************************************/
/* MEMC_GEN_0 :: SCB_START_ADDR_INTR_WRITE_CLEAR :: reserved0 [31:01] */
#define BCHP_MEMC_GEN_0_SCB_START_ADDR_INTR_WRITE_CLEAR_reserved0_MASK 0xfffffffe
#define BCHP_MEMC_GEN_0_SCB_START_ADDR_INTR_WRITE_CLEAR_reserved0_SHIFT 1

/* MEMC_GEN_0 :: SCB_START_ADDR_INTR_WRITE_CLEAR :: WRITE_CLEAR [00:00] */
#define BCHP_MEMC_GEN_0_SCB_START_ADDR_INTR_WRITE_CLEAR_WRITE_CLEAR_MASK 0x00000001
#define BCHP_MEMC_GEN_0_SCB_START_ADDR_INTR_WRITE_CLEAR_WRITE_CLEAR_SHIFT 0
#define BCHP_MEMC_GEN_0_SCB_START_ADDR_INTR_WRITE_CLEAR_WRITE_CLEAR_DEFAULT 0

/***************************************************************************
 *SCB_LAST_WRITE_ERROR_INFO - MEMC Missing SCB last write pulse error information
 ***************************************************************************/
/* MEMC_GEN_0 :: SCB_LAST_WRITE_ERROR_INFO :: CLIENTID [31:25] */
#define BCHP_MEMC_GEN_0_SCB_LAST_WRITE_ERROR_INFO_CLIENTID_MASK    0xfe000000
#define BCHP_MEMC_GEN_0_SCB_LAST_WRITE_ERROR_INFO_CLIENTID_SHIFT   25
#define BCHP_MEMC_GEN_0_SCB_LAST_WRITE_ERROR_INFO_CLIENTID_DEFAULT 0

/* MEMC_GEN_0 :: SCB_LAST_WRITE_ERROR_INFO :: NMB [24:15] */
#define BCHP_MEMC_GEN_0_SCB_LAST_WRITE_ERROR_INFO_NMB_MASK         0x01ff8000
#define BCHP_MEMC_GEN_0_SCB_LAST_WRITE_ERROR_INFO_NMB_SHIFT        15
#define BCHP_MEMC_GEN_0_SCB_LAST_WRITE_ERROR_INFO_NMB_DEFAULT      0

/* MEMC_GEN_0 :: SCB_LAST_WRITE_ERROR_INFO :: REQ_TYPE [14:06] */
#define BCHP_MEMC_GEN_0_SCB_LAST_WRITE_ERROR_INFO_REQ_TYPE_MASK    0x00007fc0
#define BCHP_MEMC_GEN_0_SCB_LAST_WRITE_ERROR_INFO_REQ_TYPE_SHIFT   6
#define BCHP_MEMC_GEN_0_SCB_LAST_WRITE_ERROR_INFO_REQ_TYPE_DEFAULT 0

/* MEMC_GEN_0 :: SCB_LAST_WRITE_ERROR_INFO :: ADDR [05:00] */
#define BCHP_MEMC_GEN_0_SCB_LAST_WRITE_ERROR_INFO_ADDR_MASK        0x0000003f
#define BCHP_MEMC_GEN_0_SCB_LAST_WRITE_ERROR_INFO_ADDR_SHIFT       0
#define BCHP_MEMC_GEN_0_SCB_LAST_WRITE_ERROR_INFO_ADDR_DEFAULT     0

/***************************************************************************
 *SCB_LAST_WRITE_ERROR_WRITE_CLEAR - MEMC scb Missing SCB last write pulse write clear register
 ***************************************************************************/
/* MEMC_GEN_0 :: SCB_LAST_WRITE_ERROR_WRITE_CLEAR :: reserved0 [31:01] */
#define BCHP_MEMC_GEN_0_SCB_LAST_WRITE_ERROR_WRITE_CLEAR_reserved0_MASK 0xfffffffe
#define BCHP_MEMC_GEN_0_SCB_LAST_WRITE_ERROR_WRITE_CLEAR_reserved0_SHIFT 1

/* MEMC_GEN_0 :: SCB_LAST_WRITE_ERROR_WRITE_CLEAR :: WRITE_CLEAR [00:00] */
#define BCHP_MEMC_GEN_0_SCB_LAST_WRITE_ERROR_WRITE_CLEAR_WRITE_CLEAR_MASK 0x00000001
#define BCHP_MEMC_GEN_0_SCB_LAST_WRITE_ERROR_WRITE_CLEAR_WRITE_CLEAR_SHIFT 0
#define BCHP_MEMC_GEN_0_SCB_LAST_WRITE_ERROR_WRITE_CLEAR_WRITE_CLEAR_DEFAULT 0

/***************************************************************************
 *CMD_TRACE_FIFO_MODE - Mode of the SCB command trace FIFO
 ***************************************************************************/
/* MEMC_GEN_0 :: CMD_TRACE_FIFO_MODE :: reserved0 [31:17] */
#define BCHP_MEMC_GEN_0_CMD_TRACE_FIFO_MODE_reserved0_MASK         0xfffe0000
#define BCHP_MEMC_GEN_0_CMD_TRACE_FIFO_MODE_reserved0_SHIFT        17

/* MEMC_GEN_0 :: CMD_TRACE_FIFO_MODE :: UNFREEZE [16:16] */
#define BCHP_MEMC_GEN_0_CMD_TRACE_FIFO_MODE_UNFREEZE_MASK          0x00010000
#define BCHP_MEMC_GEN_0_CMD_TRACE_FIFO_MODE_UNFREEZE_SHIFT         16
#define BCHP_MEMC_GEN_0_CMD_TRACE_FIFO_MODE_UNFREEZE_DEFAULT       0

/* MEMC_GEN_0 :: CMD_TRACE_FIFO_MODE :: reserved1 [15:13] */
#define BCHP_MEMC_GEN_0_CMD_TRACE_FIFO_MODE_reserved1_MASK         0x0000e000
#define BCHP_MEMC_GEN_0_CMD_TRACE_FIFO_MODE_reserved1_SHIFT        13

/* MEMC_GEN_0 :: CMD_TRACE_FIFO_MODE :: TRIG_SMTO [12:12] */
#define BCHP_MEMC_GEN_0_CMD_TRACE_FIFO_MODE_TRIG_SMTO_MASK         0x00001000
#define BCHP_MEMC_GEN_0_CMD_TRACE_FIFO_MODE_TRIG_SMTO_SHIFT        12
#define BCHP_MEMC_GEN_0_CMD_TRACE_FIFO_MODE_TRIG_SMTO_DEFAULT      0

/* MEMC_GEN_0 :: CMD_TRACE_FIFO_MODE :: TRIG_NOREQ [11:11] */
#define BCHP_MEMC_GEN_0_CMD_TRACE_FIFO_MODE_TRIG_NOREQ_MASK        0x00000800
#define BCHP_MEMC_GEN_0_CMD_TRACE_FIFO_MODE_TRIG_NOREQ_SHIFT       11
#define BCHP_MEMC_GEN_0_CMD_TRACE_FIFO_MODE_TRIG_NOREQ_DEFAULT     0

/* MEMC_GEN_0 :: CMD_TRACE_FIFO_MODE :: TRIG_INV_CMD [10:10] */
#define BCHP_MEMC_GEN_0_CMD_TRACE_FIFO_MODE_TRIG_INV_CMD_MASK      0x00000400
#define BCHP_MEMC_GEN_0_CMD_TRACE_FIFO_MODE_TRIG_INV_CMD_SHIFT     10
#define BCHP_MEMC_GEN_0_CMD_TRACE_FIFO_MODE_TRIG_INV_CMD_DEFAULT   0

/* MEMC_GEN_0 :: CMD_TRACE_FIFO_MODE :: TRIG_INV_NMB [09:09] */
#define BCHP_MEMC_GEN_0_CMD_TRACE_FIFO_MODE_TRIG_INV_NMB_MASK      0x00000200
#define BCHP_MEMC_GEN_0_CMD_TRACE_FIFO_MODE_TRIG_INV_NMB_SHIFT     9
#define BCHP_MEMC_GEN_0_CMD_TRACE_FIFO_MODE_TRIG_INV_NMB_DEFAULT   0

/* MEMC_GEN_0 :: CMD_TRACE_FIFO_MODE :: TRIG_START_ADDR [08:08] */
#define BCHP_MEMC_GEN_0_CMD_TRACE_FIFO_MODE_TRIG_START_ADDR_MASK   0x00000100
#define BCHP_MEMC_GEN_0_CMD_TRACE_FIFO_MODE_TRIG_START_ADDR_SHIFT  8
#define BCHP_MEMC_GEN_0_CMD_TRACE_FIFO_MODE_TRIG_START_ADDR_DEFAULT 0

/* MEMC_GEN_0 :: CMD_TRACE_FIFO_MODE :: reserved2 [07:04] */
#define BCHP_MEMC_GEN_0_CMD_TRACE_FIFO_MODE_reserved2_MASK         0x000000f0
#define BCHP_MEMC_GEN_0_CMD_TRACE_FIFO_MODE_reserved2_SHIFT        4

/* MEMC_GEN_0 :: CMD_TRACE_FIFO_MODE :: TRIG_ARC3 [03:03] */
#define BCHP_MEMC_GEN_0_CMD_TRACE_FIFO_MODE_TRIG_ARC3_MASK         0x00000008
#define BCHP_MEMC_GEN_0_CMD_TRACE_FIFO_MODE_TRIG_ARC3_SHIFT        3
#define BCHP_MEMC_GEN_0_CMD_TRACE_FIFO_MODE_TRIG_ARC3_DEFAULT      0

/* MEMC_GEN_0 :: CMD_TRACE_FIFO_MODE :: TRIG_ARC2 [02:02] */
#define BCHP_MEMC_GEN_0_CMD_TRACE_FIFO_MODE_TRIG_ARC2_MASK         0x00000004
#define BCHP_MEMC_GEN_0_CMD_TRACE_FIFO_MODE_TRIG_ARC2_SHIFT        2
#define BCHP_MEMC_GEN_0_CMD_TRACE_FIFO_MODE_TRIG_ARC2_DEFAULT      0

/* MEMC_GEN_0 :: CMD_TRACE_FIFO_MODE :: TRIG_ARC1 [01:01] */
#define BCHP_MEMC_GEN_0_CMD_TRACE_FIFO_MODE_TRIG_ARC1_MASK         0x00000002
#define BCHP_MEMC_GEN_0_CMD_TRACE_FIFO_MODE_TRIG_ARC1_SHIFT        1
#define BCHP_MEMC_GEN_0_CMD_TRACE_FIFO_MODE_TRIG_ARC1_DEFAULT      0

/* MEMC_GEN_0 :: CMD_TRACE_FIFO_MODE :: TRIG_ARC0 [00:00] */
#define BCHP_MEMC_GEN_0_CMD_TRACE_FIFO_MODE_TRIG_ARC0_MASK         0x00000001
#define BCHP_MEMC_GEN_0_CMD_TRACE_FIFO_MODE_TRIG_ARC0_SHIFT        0
#define BCHP_MEMC_GEN_0_CMD_TRACE_FIFO_MODE_TRIG_ARC0_DEFAULT      0

/***************************************************************************
 *SEQ_CMD_DBG_0 - Current DATA command pushed out from sequencer.
 ***************************************************************************/
/* MEMC_GEN_0 :: SEQ_CMD_DBG_0 :: reserved0 [31:22] */
#define BCHP_MEMC_GEN_0_SEQ_CMD_DBG_0_reserved0_MASK               0xffc00000
#define BCHP_MEMC_GEN_0_SEQ_CMD_DBG_0_reserved0_SHIFT              22

/* MEMC_GEN_0 :: SEQ_CMD_DBG_0 :: CAS1_LAST [21:21] */
#define BCHP_MEMC_GEN_0_SEQ_CMD_DBG_0_CAS1_LAST_MASK               0x00200000
#define BCHP_MEMC_GEN_0_SEQ_CMD_DBG_0_CAS1_LAST_SHIFT              21
#define BCHP_MEMC_GEN_0_SEQ_CMD_DBG_0_CAS1_LAST_DEFAULT            0

/* MEMC_GEN_0 :: SEQ_CMD_DBG_0 :: CAS1_AP [20:20] */
#define BCHP_MEMC_GEN_0_SEQ_CMD_DBG_0_CAS1_AP_MASK                 0x00100000
#define BCHP_MEMC_GEN_0_SEQ_CMD_DBG_0_CAS1_AP_SHIFT                20
#define BCHP_MEMC_GEN_0_SEQ_CMD_DBG_0_CAS1_AP_DEFAULT              0

/* MEMC_GEN_0 :: SEQ_CMD_DBG_0 :: CAS1_BANK_ADDR [19:17] */
#define BCHP_MEMC_GEN_0_SEQ_CMD_DBG_0_CAS1_BANK_ADDR_MASK          0x000e0000
#define BCHP_MEMC_GEN_0_SEQ_CMD_DBG_0_CAS1_BANK_ADDR_SHIFT         17
#define BCHP_MEMC_GEN_0_SEQ_CMD_DBG_0_CAS1_BANK_ADDR_DEFAULT       0

/* MEMC_GEN_0 :: SEQ_CMD_DBG_0 :: CAS1_POSITION [16:15] */
#define BCHP_MEMC_GEN_0_SEQ_CMD_DBG_0_CAS1_POSITION_MASK           0x00018000
#define BCHP_MEMC_GEN_0_SEQ_CMD_DBG_0_CAS1_POSITION_SHIFT          15
#define BCHP_MEMC_GEN_0_SEQ_CMD_DBG_0_CAS1_POSITION_DEFAULT        0

/* MEMC_GEN_0 :: SEQ_CMD_DBG_0 :: CAS1_ISSUED [14:14] */
#define BCHP_MEMC_GEN_0_SEQ_CMD_DBG_0_CAS1_ISSUED_MASK             0x00004000
#define BCHP_MEMC_GEN_0_SEQ_CMD_DBG_0_CAS1_ISSUED_SHIFT            14
#define BCHP_MEMC_GEN_0_SEQ_CMD_DBG_0_CAS1_ISSUED_DEFAULT          0

/* MEMC_GEN_0 :: SEQ_CMD_DBG_0 :: CAS0_LAST [13:13] */
#define BCHP_MEMC_GEN_0_SEQ_CMD_DBG_0_CAS0_LAST_MASK               0x00002000
#define BCHP_MEMC_GEN_0_SEQ_CMD_DBG_0_CAS0_LAST_SHIFT              13
#define BCHP_MEMC_GEN_0_SEQ_CMD_DBG_0_CAS0_LAST_DEFAULT            0

/* MEMC_GEN_0 :: SEQ_CMD_DBG_0 :: CAS0_AP [12:12] */
#define BCHP_MEMC_GEN_0_SEQ_CMD_DBG_0_CAS0_AP_MASK                 0x00001000
#define BCHP_MEMC_GEN_0_SEQ_CMD_DBG_0_CAS0_AP_SHIFT                12
#define BCHP_MEMC_GEN_0_SEQ_CMD_DBG_0_CAS0_AP_DEFAULT              0

/* MEMC_GEN_0 :: SEQ_CMD_DBG_0 :: CAS0_BANK_ADDR [11:09] */
#define BCHP_MEMC_GEN_0_SEQ_CMD_DBG_0_CAS0_BANK_ADDR_MASK          0x00000e00
#define BCHP_MEMC_GEN_0_SEQ_CMD_DBG_0_CAS0_BANK_ADDR_SHIFT         9
#define BCHP_MEMC_GEN_0_SEQ_CMD_DBG_0_CAS0_BANK_ADDR_DEFAULT       0

/* MEMC_GEN_0 :: SEQ_CMD_DBG_0 :: CAS0_POSITION [08:07] */
#define BCHP_MEMC_GEN_0_SEQ_CMD_DBG_0_CAS0_POSITION_MASK           0x00000180
#define BCHP_MEMC_GEN_0_SEQ_CMD_DBG_0_CAS0_POSITION_SHIFT          7
#define BCHP_MEMC_GEN_0_SEQ_CMD_DBG_0_CAS0_POSITION_DEFAULT        0

/* MEMC_GEN_0 :: SEQ_CMD_DBG_0 :: CAS0_ISSUED [06:06] */
#define BCHP_MEMC_GEN_0_SEQ_CMD_DBG_0_CAS0_ISSUED_MASK             0x00000040
#define BCHP_MEMC_GEN_0_SEQ_CMD_DBG_0_CAS0_ISSUED_SHIFT            6
#define BCHP_MEMC_GEN_0_SEQ_CMD_DBG_0_CAS0_ISSUED_DEFAULT          0

/* MEMC_GEN_0 :: SEQ_CMD_DBG_0 :: RAS_BANK_ADDR [05:03] */
#define BCHP_MEMC_GEN_0_SEQ_CMD_DBG_0_RAS_BANK_ADDR_MASK           0x00000038
#define BCHP_MEMC_GEN_0_SEQ_CMD_DBG_0_RAS_BANK_ADDR_SHIFT          3
#define BCHP_MEMC_GEN_0_SEQ_CMD_DBG_0_RAS_BANK_ADDR_DEFAULT        0

/* MEMC_GEN_0 :: SEQ_CMD_DBG_0 :: RAS_POSITION [02:01] */
#define BCHP_MEMC_GEN_0_SEQ_CMD_DBG_0_RAS_POSITION_MASK            0x00000006
#define BCHP_MEMC_GEN_0_SEQ_CMD_DBG_0_RAS_POSITION_SHIFT           1
#define BCHP_MEMC_GEN_0_SEQ_CMD_DBG_0_RAS_POSITION_DEFAULT         0

/* MEMC_GEN_0 :: SEQ_CMD_DBG_0 :: RAS_ISSUED [00:00] */
#define BCHP_MEMC_GEN_0_SEQ_CMD_DBG_0_RAS_ISSUED_MASK              0x00000001
#define BCHP_MEMC_GEN_0_SEQ_CMD_DBG_0_RAS_ISSUED_SHIFT             0
#define BCHP_MEMC_GEN_0_SEQ_CMD_DBG_0_RAS_ISSUED_DEFAULT           0

/***************************************************************************
 *SEQ_CMD_DBG_1 - Current DATA command pushed out from sequencer.
 ***************************************************************************/
/* MEMC_GEN_0 :: SEQ_CMD_DBG_1 :: reserved0 [31:22] */
#define BCHP_MEMC_GEN_0_SEQ_CMD_DBG_1_reserved0_MASK               0xffc00000
#define BCHP_MEMC_GEN_0_SEQ_CMD_DBG_1_reserved0_SHIFT              22

/* MEMC_GEN_0 :: SEQ_CMD_DBG_1 :: CAS1_LAST [21:21] */
#define BCHP_MEMC_GEN_0_SEQ_CMD_DBG_1_CAS1_LAST_MASK               0x00200000
#define BCHP_MEMC_GEN_0_SEQ_CMD_DBG_1_CAS1_LAST_SHIFT              21
#define BCHP_MEMC_GEN_0_SEQ_CMD_DBG_1_CAS1_LAST_DEFAULT            0

/* MEMC_GEN_0 :: SEQ_CMD_DBG_1 :: CAS1_AP [20:20] */
#define BCHP_MEMC_GEN_0_SEQ_CMD_DBG_1_CAS1_AP_MASK                 0x00100000
#define BCHP_MEMC_GEN_0_SEQ_CMD_DBG_1_CAS1_AP_SHIFT                20
#define BCHP_MEMC_GEN_0_SEQ_CMD_DBG_1_CAS1_AP_DEFAULT              0

/* MEMC_GEN_0 :: SEQ_CMD_DBG_1 :: CAS1_BANK_ADDR [19:17] */
#define BCHP_MEMC_GEN_0_SEQ_CMD_DBG_1_CAS1_BANK_ADDR_MASK          0x000e0000
#define BCHP_MEMC_GEN_0_SEQ_CMD_DBG_1_CAS1_BANK_ADDR_SHIFT         17
#define BCHP_MEMC_GEN_0_SEQ_CMD_DBG_1_CAS1_BANK_ADDR_DEFAULT       0

/* MEMC_GEN_0 :: SEQ_CMD_DBG_1 :: CAS1_POSITION [16:15] */
#define BCHP_MEMC_GEN_0_SEQ_CMD_DBG_1_CAS1_POSITION_MASK           0x00018000
#define BCHP_MEMC_GEN_0_SEQ_CMD_DBG_1_CAS1_POSITION_SHIFT          15
#define BCHP_MEMC_GEN_0_SEQ_CMD_DBG_1_CAS1_POSITION_DEFAULT        0

/* MEMC_GEN_0 :: SEQ_CMD_DBG_1 :: CAS1_ISSUED [14:14] */
#define BCHP_MEMC_GEN_0_SEQ_CMD_DBG_1_CAS1_ISSUED_MASK             0x00004000
#define BCHP_MEMC_GEN_0_SEQ_CMD_DBG_1_CAS1_ISSUED_SHIFT            14
#define BCHP_MEMC_GEN_0_SEQ_CMD_DBG_1_CAS1_ISSUED_DEFAULT          0

/* MEMC_GEN_0 :: SEQ_CMD_DBG_1 :: CAS0_LAST [13:13] */
#define BCHP_MEMC_GEN_0_SEQ_CMD_DBG_1_CAS0_LAST_MASK               0x00002000
#define BCHP_MEMC_GEN_0_SEQ_CMD_DBG_1_CAS0_LAST_SHIFT              13
#define BCHP_MEMC_GEN_0_SEQ_CMD_DBG_1_CAS0_LAST_DEFAULT            0

/* MEMC_GEN_0 :: SEQ_CMD_DBG_1 :: CAS0_AP [12:12] */
#define BCHP_MEMC_GEN_0_SEQ_CMD_DBG_1_CAS0_AP_MASK                 0x00001000
#define BCHP_MEMC_GEN_0_SEQ_CMD_DBG_1_CAS0_AP_SHIFT                12
#define BCHP_MEMC_GEN_0_SEQ_CMD_DBG_1_CAS0_AP_DEFAULT              0

/* MEMC_GEN_0 :: SEQ_CMD_DBG_1 :: CAS0_BANK_ADDR [11:09] */
#define BCHP_MEMC_GEN_0_SEQ_CMD_DBG_1_CAS0_BANK_ADDR_MASK          0x00000e00
#define BCHP_MEMC_GEN_0_SEQ_CMD_DBG_1_CAS0_BANK_ADDR_SHIFT         9
#define BCHP_MEMC_GEN_0_SEQ_CMD_DBG_1_CAS0_BANK_ADDR_DEFAULT       0

/* MEMC_GEN_0 :: SEQ_CMD_DBG_1 :: CAS0_POSITION [08:07] */
#define BCHP_MEMC_GEN_0_SEQ_CMD_DBG_1_CAS0_POSITION_MASK           0x00000180
#define BCHP_MEMC_GEN_0_SEQ_CMD_DBG_1_CAS0_POSITION_SHIFT          7
#define BCHP_MEMC_GEN_0_SEQ_CMD_DBG_1_CAS0_POSITION_DEFAULT        0

/* MEMC_GEN_0 :: SEQ_CMD_DBG_1 :: CAS0_ISSUED [06:06] */
#define BCHP_MEMC_GEN_0_SEQ_CMD_DBG_1_CAS0_ISSUED_MASK             0x00000040
#define BCHP_MEMC_GEN_0_SEQ_CMD_DBG_1_CAS0_ISSUED_SHIFT            6
#define BCHP_MEMC_GEN_0_SEQ_CMD_DBG_1_CAS0_ISSUED_DEFAULT          0

/* MEMC_GEN_0 :: SEQ_CMD_DBG_1 :: RAS_BANK_ADDR [05:03] */
#define BCHP_MEMC_GEN_0_SEQ_CMD_DBG_1_RAS_BANK_ADDR_MASK           0x00000038
#define BCHP_MEMC_GEN_0_SEQ_CMD_DBG_1_RAS_BANK_ADDR_SHIFT          3
#define BCHP_MEMC_GEN_0_SEQ_CMD_DBG_1_RAS_BANK_ADDR_DEFAULT        0

/* MEMC_GEN_0 :: SEQ_CMD_DBG_1 :: RAS_POSITION [02:01] */
#define BCHP_MEMC_GEN_0_SEQ_CMD_DBG_1_RAS_POSITION_MASK            0x00000006
#define BCHP_MEMC_GEN_0_SEQ_CMD_DBG_1_RAS_POSITION_SHIFT           1
#define BCHP_MEMC_GEN_0_SEQ_CMD_DBG_1_RAS_POSITION_DEFAULT         0

/* MEMC_GEN_0 :: SEQ_CMD_DBG_1 :: RAS_ISSUED [00:00] */
#define BCHP_MEMC_GEN_0_SEQ_CMD_DBG_1_RAS_ISSUED_MASK              0x00000001
#define BCHP_MEMC_GEN_0_SEQ_CMD_DBG_1_RAS_ISSUED_SHIFT             0
#define BCHP_MEMC_GEN_0_SEQ_CMD_DBG_1_RAS_ISSUED_DEFAULT           0

/***************************************************************************
 *SEQ_CMD_DBG_2 - Current DATA command pushed out from sequencer.
 ***************************************************************************/
/* MEMC_GEN_0 :: SEQ_CMD_DBG_2 :: reserved0 [31:22] */
#define BCHP_MEMC_GEN_0_SEQ_CMD_DBG_2_reserved0_MASK               0xffc00000
#define BCHP_MEMC_GEN_0_SEQ_CMD_DBG_2_reserved0_SHIFT              22

/* MEMC_GEN_0 :: SEQ_CMD_DBG_2 :: CAS1_LAST [21:21] */
#define BCHP_MEMC_GEN_0_SEQ_CMD_DBG_2_CAS1_LAST_MASK               0x00200000
#define BCHP_MEMC_GEN_0_SEQ_CMD_DBG_2_CAS1_LAST_SHIFT              21
#define BCHP_MEMC_GEN_0_SEQ_CMD_DBG_2_CAS1_LAST_DEFAULT            0

/* MEMC_GEN_0 :: SEQ_CMD_DBG_2 :: CAS1_AP [20:20] */
#define BCHP_MEMC_GEN_0_SEQ_CMD_DBG_2_CAS1_AP_MASK                 0x00100000
#define BCHP_MEMC_GEN_0_SEQ_CMD_DBG_2_CAS1_AP_SHIFT                20
#define BCHP_MEMC_GEN_0_SEQ_CMD_DBG_2_CAS1_AP_DEFAULT              0

/* MEMC_GEN_0 :: SEQ_CMD_DBG_2 :: CAS1_BANK_ADDR [19:17] */
#define BCHP_MEMC_GEN_0_SEQ_CMD_DBG_2_CAS1_BANK_ADDR_MASK          0x000e0000
#define BCHP_MEMC_GEN_0_SEQ_CMD_DBG_2_CAS1_BANK_ADDR_SHIFT         17
#define BCHP_MEMC_GEN_0_SEQ_CMD_DBG_2_CAS1_BANK_ADDR_DEFAULT       0

/* MEMC_GEN_0 :: SEQ_CMD_DBG_2 :: CAS1_POSITION [16:15] */
#define BCHP_MEMC_GEN_0_SEQ_CMD_DBG_2_CAS1_POSITION_MASK           0x00018000
#define BCHP_MEMC_GEN_0_SEQ_CMD_DBG_2_CAS1_POSITION_SHIFT          15
#define BCHP_MEMC_GEN_0_SEQ_CMD_DBG_2_CAS1_POSITION_DEFAULT        0

/* MEMC_GEN_0 :: SEQ_CMD_DBG_2 :: CAS1_ISSUED [14:14] */
#define BCHP_MEMC_GEN_0_SEQ_CMD_DBG_2_CAS1_ISSUED_MASK             0x00004000
#define BCHP_MEMC_GEN_0_SEQ_CMD_DBG_2_CAS1_ISSUED_SHIFT            14
#define BCHP_MEMC_GEN_0_SEQ_CMD_DBG_2_CAS1_ISSUED_DEFAULT          0

/* MEMC_GEN_0 :: SEQ_CMD_DBG_2 :: CAS0_LAST [13:13] */
#define BCHP_MEMC_GEN_0_SEQ_CMD_DBG_2_CAS0_LAST_MASK               0x00002000
#define BCHP_MEMC_GEN_0_SEQ_CMD_DBG_2_CAS0_LAST_SHIFT              13
#define BCHP_MEMC_GEN_0_SEQ_CMD_DBG_2_CAS0_LAST_DEFAULT            0

/* MEMC_GEN_0 :: SEQ_CMD_DBG_2 :: CAS0_AP [12:12] */
#define BCHP_MEMC_GEN_0_SEQ_CMD_DBG_2_CAS0_AP_MASK                 0x00001000
#define BCHP_MEMC_GEN_0_SEQ_CMD_DBG_2_CAS0_AP_SHIFT                12
#define BCHP_MEMC_GEN_0_SEQ_CMD_DBG_2_CAS0_AP_DEFAULT              0

/* MEMC_GEN_0 :: SEQ_CMD_DBG_2 :: CAS0_BANK_ADDR [11:09] */
#define BCHP_MEMC_GEN_0_SEQ_CMD_DBG_2_CAS0_BANK_ADDR_MASK          0x00000e00
#define BCHP_MEMC_GEN_0_SEQ_CMD_DBG_2_CAS0_BANK_ADDR_SHIFT         9
#define BCHP_MEMC_GEN_0_SEQ_CMD_DBG_2_CAS0_BANK_ADDR_DEFAULT       0

/* MEMC_GEN_0 :: SEQ_CMD_DBG_2 :: CAS0_POSITION [08:07] */
#define BCHP_MEMC_GEN_0_SEQ_CMD_DBG_2_CAS0_POSITION_MASK           0x00000180
#define BCHP_MEMC_GEN_0_SEQ_CMD_DBG_2_CAS0_POSITION_SHIFT          7
#define BCHP_MEMC_GEN_0_SEQ_CMD_DBG_2_CAS0_POSITION_DEFAULT        0

/* MEMC_GEN_0 :: SEQ_CMD_DBG_2 :: CAS0_ISSUED [06:06] */
#define BCHP_MEMC_GEN_0_SEQ_CMD_DBG_2_CAS0_ISSUED_MASK             0x00000040
#define BCHP_MEMC_GEN_0_SEQ_CMD_DBG_2_CAS0_ISSUED_SHIFT            6
#define BCHP_MEMC_GEN_0_SEQ_CMD_DBG_2_CAS0_ISSUED_DEFAULT          0

/* MEMC_GEN_0 :: SEQ_CMD_DBG_2 :: RAS_BANK_ADDR [05:03] */
#define BCHP_MEMC_GEN_0_SEQ_CMD_DBG_2_RAS_BANK_ADDR_MASK           0x00000038
#define BCHP_MEMC_GEN_0_SEQ_CMD_DBG_2_RAS_BANK_ADDR_SHIFT          3
#define BCHP_MEMC_GEN_0_SEQ_CMD_DBG_2_RAS_BANK_ADDR_DEFAULT        0

/* MEMC_GEN_0 :: SEQ_CMD_DBG_2 :: RAS_POSITION [02:01] */
#define BCHP_MEMC_GEN_0_SEQ_CMD_DBG_2_RAS_POSITION_MASK            0x00000006
#define BCHP_MEMC_GEN_0_SEQ_CMD_DBG_2_RAS_POSITION_SHIFT           1
#define BCHP_MEMC_GEN_0_SEQ_CMD_DBG_2_RAS_POSITION_DEFAULT         0

/* MEMC_GEN_0 :: SEQ_CMD_DBG_2 :: RAS_ISSUED [00:00] */
#define BCHP_MEMC_GEN_0_SEQ_CMD_DBG_2_RAS_ISSUED_MASK              0x00000001
#define BCHP_MEMC_GEN_0_SEQ_CMD_DBG_2_RAS_ISSUED_SHIFT             0
#define BCHP_MEMC_GEN_0_SEQ_CMD_DBG_2_RAS_ISSUED_DEFAULT           0

/***************************************************************************
 *SEQ_CMD_DBG_3 - Current DATA command pushed out from sequencer.
 ***************************************************************************/
/* MEMC_GEN_0 :: SEQ_CMD_DBG_3 :: reserved0 [31:22] */
#define BCHP_MEMC_GEN_0_SEQ_CMD_DBG_3_reserved0_MASK               0xffc00000
#define BCHP_MEMC_GEN_0_SEQ_CMD_DBG_3_reserved0_SHIFT              22

/* MEMC_GEN_0 :: SEQ_CMD_DBG_3 :: CAS1_LAST [21:21] */
#define BCHP_MEMC_GEN_0_SEQ_CMD_DBG_3_CAS1_LAST_MASK               0x00200000
#define BCHP_MEMC_GEN_0_SEQ_CMD_DBG_3_CAS1_LAST_SHIFT              21
#define BCHP_MEMC_GEN_0_SEQ_CMD_DBG_3_CAS1_LAST_DEFAULT            0

/* MEMC_GEN_0 :: SEQ_CMD_DBG_3 :: CAS1_AP [20:20] */
#define BCHP_MEMC_GEN_0_SEQ_CMD_DBG_3_CAS1_AP_MASK                 0x00100000
#define BCHP_MEMC_GEN_0_SEQ_CMD_DBG_3_CAS1_AP_SHIFT                20
#define BCHP_MEMC_GEN_0_SEQ_CMD_DBG_3_CAS1_AP_DEFAULT              0

/* MEMC_GEN_0 :: SEQ_CMD_DBG_3 :: CAS1_BANK_ADDR [19:17] */
#define BCHP_MEMC_GEN_0_SEQ_CMD_DBG_3_CAS1_BANK_ADDR_MASK          0x000e0000
#define BCHP_MEMC_GEN_0_SEQ_CMD_DBG_3_CAS1_BANK_ADDR_SHIFT         17
#define BCHP_MEMC_GEN_0_SEQ_CMD_DBG_3_CAS1_BANK_ADDR_DEFAULT       0

/* MEMC_GEN_0 :: SEQ_CMD_DBG_3 :: CAS1_POSITION [16:15] */
#define BCHP_MEMC_GEN_0_SEQ_CMD_DBG_3_CAS1_POSITION_MASK           0x00018000
#define BCHP_MEMC_GEN_0_SEQ_CMD_DBG_3_CAS1_POSITION_SHIFT          15
#define BCHP_MEMC_GEN_0_SEQ_CMD_DBG_3_CAS1_POSITION_DEFAULT        0

/* MEMC_GEN_0 :: SEQ_CMD_DBG_3 :: CAS1_ISSUED [14:14] */
#define BCHP_MEMC_GEN_0_SEQ_CMD_DBG_3_CAS1_ISSUED_MASK             0x00004000
#define BCHP_MEMC_GEN_0_SEQ_CMD_DBG_3_CAS1_ISSUED_SHIFT            14
#define BCHP_MEMC_GEN_0_SEQ_CMD_DBG_3_CAS1_ISSUED_DEFAULT          0

/* MEMC_GEN_0 :: SEQ_CMD_DBG_3 :: CAS0_LAST [13:13] */
#define BCHP_MEMC_GEN_0_SEQ_CMD_DBG_3_CAS0_LAST_MASK               0x00002000
#define BCHP_MEMC_GEN_0_SEQ_CMD_DBG_3_CAS0_LAST_SHIFT              13
#define BCHP_MEMC_GEN_0_SEQ_CMD_DBG_3_CAS0_LAST_DEFAULT            0

/* MEMC_GEN_0 :: SEQ_CMD_DBG_3 :: CAS0_AP [12:12] */
#define BCHP_MEMC_GEN_0_SEQ_CMD_DBG_3_CAS0_AP_MASK                 0x00001000
#define BCHP_MEMC_GEN_0_SEQ_CMD_DBG_3_CAS0_AP_SHIFT                12
#define BCHP_MEMC_GEN_0_SEQ_CMD_DBG_3_CAS0_AP_DEFAULT              0

/* MEMC_GEN_0 :: SEQ_CMD_DBG_3 :: CAS0_BANK_ADDR [11:09] */
#define BCHP_MEMC_GEN_0_SEQ_CMD_DBG_3_CAS0_BANK_ADDR_MASK          0x00000e00
#define BCHP_MEMC_GEN_0_SEQ_CMD_DBG_3_CAS0_BANK_ADDR_SHIFT         9
#define BCHP_MEMC_GEN_0_SEQ_CMD_DBG_3_CAS0_BANK_ADDR_DEFAULT       0

/* MEMC_GEN_0 :: SEQ_CMD_DBG_3 :: CAS0_POSITION [08:07] */
#define BCHP_MEMC_GEN_0_SEQ_CMD_DBG_3_CAS0_POSITION_MASK           0x00000180
#define BCHP_MEMC_GEN_0_SEQ_CMD_DBG_3_CAS0_POSITION_SHIFT          7
#define BCHP_MEMC_GEN_0_SEQ_CMD_DBG_3_CAS0_POSITION_DEFAULT        0

/* MEMC_GEN_0 :: SEQ_CMD_DBG_3 :: CAS0_ISSUED [06:06] */
#define BCHP_MEMC_GEN_0_SEQ_CMD_DBG_3_CAS0_ISSUED_MASK             0x00000040
#define BCHP_MEMC_GEN_0_SEQ_CMD_DBG_3_CAS0_ISSUED_SHIFT            6
#define BCHP_MEMC_GEN_0_SEQ_CMD_DBG_3_CAS0_ISSUED_DEFAULT          0

/* MEMC_GEN_0 :: SEQ_CMD_DBG_3 :: RAS_BANK_ADDR [05:03] */
#define BCHP_MEMC_GEN_0_SEQ_CMD_DBG_3_RAS_BANK_ADDR_MASK           0x00000038
#define BCHP_MEMC_GEN_0_SEQ_CMD_DBG_3_RAS_BANK_ADDR_SHIFT          3
#define BCHP_MEMC_GEN_0_SEQ_CMD_DBG_3_RAS_BANK_ADDR_DEFAULT        0

/* MEMC_GEN_0 :: SEQ_CMD_DBG_3 :: RAS_POSITION [02:01] */
#define BCHP_MEMC_GEN_0_SEQ_CMD_DBG_3_RAS_POSITION_MASK            0x00000006
#define BCHP_MEMC_GEN_0_SEQ_CMD_DBG_3_RAS_POSITION_SHIFT           1
#define BCHP_MEMC_GEN_0_SEQ_CMD_DBG_3_RAS_POSITION_DEFAULT         0

/* MEMC_GEN_0 :: SEQ_CMD_DBG_3 :: RAS_ISSUED [00:00] */
#define BCHP_MEMC_GEN_0_SEQ_CMD_DBG_3_RAS_ISSUED_MASK              0x00000001
#define BCHP_MEMC_GEN_0_SEQ_CMD_DBG_3_RAS_ISSUED_SHIFT             0
#define BCHP_MEMC_GEN_0_SEQ_CMD_DBG_3_RAS_ISSUED_DEFAULT           0

/***************************************************************************
 *SEQ_CMD_DBG_4 - Current DATA command pushed out from sequencer.
 ***************************************************************************/
/* MEMC_GEN_0 :: SEQ_CMD_DBG_4 :: reserved0 [31:22] */
#define BCHP_MEMC_GEN_0_SEQ_CMD_DBG_4_reserved0_MASK               0xffc00000
#define BCHP_MEMC_GEN_0_SEQ_CMD_DBG_4_reserved0_SHIFT              22

/* MEMC_GEN_0 :: SEQ_CMD_DBG_4 :: CAS1_LAST [21:21] */
#define BCHP_MEMC_GEN_0_SEQ_CMD_DBG_4_CAS1_LAST_MASK               0x00200000
#define BCHP_MEMC_GEN_0_SEQ_CMD_DBG_4_CAS1_LAST_SHIFT              21
#define BCHP_MEMC_GEN_0_SEQ_CMD_DBG_4_CAS1_LAST_DEFAULT            0

/* MEMC_GEN_0 :: SEQ_CMD_DBG_4 :: CAS1_AP [20:20] */
#define BCHP_MEMC_GEN_0_SEQ_CMD_DBG_4_CAS1_AP_MASK                 0x00100000
#define BCHP_MEMC_GEN_0_SEQ_CMD_DBG_4_CAS1_AP_SHIFT                20
#define BCHP_MEMC_GEN_0_SEQ_CMD_DBG_4_CAS1_AP_DEFAULT              0

/* MEMC_GEN_0 :: SEQ_CMD_DBG_4 :: CAS1_BANK_ADDR [19:17] */
#define BCHP_MEMC_GEN_0_SEQ_CMD_DBG_4_CAS1_BANK_ADDR_MASK          0x000e0000
#define BCHP_MEMC_GEN_0_SEQ_CMD_DBG_4_CAS1_BANK_ADDR_SHIFT         17
#define BCHP_MEMC_GEN_0_SEQ_CMD_DBG_4_CAS1_BANK_ADDR_DEFAULT       0

/* MEMC_GEN_0 :: SEQ_CMD_DBG_4 :: CAS1_POSITION [16:15] */
#define BCHP_MEMC_GEN_0_SEQ_CMD_DBG_4_CAS1_POSITION_MASK           0x00018000
#define BCHP_MEMC_GEN_0_SEQ_CMD_DBG_4_CAS1_POSITION_SHIFT          15
#define BCHP_MEMC_GEN_0_SEQ_CMD_DBG_4_CAS1_POSITION_DEFAULT        0

/* MEMC_GEN_0 :: SEQ_CMD_DBG_4 :: CAS1_ISSUED [14:14] */
#define BCHP_MEMC_GEN_0_SEQ_CMD_DBG_4_CAS1_ISSUED_MASK             0x00004000
#define BCHP_MEMC_GEN_0_SEQ_CMD_DBG_4_CAS1_ISSUED_SHIFT            14
#define BCHP_MEMC_GEN_0_SEQ_CMD_DBG_4_CAS1_ISSUED_DEFAULT          0

/* MEMC_GEN_0 :: SEQ_CMD_DBG_4 :: CAS0_LAST [13:13] */
#define BCHP_MEMC_GEN_0_SEQ_CMD_DBG_4_CAS0_LAST_MASK               0x00002000
#define BCHP_MEMC_GEN_0_SEQ_CMD_DBG_4_CAS0_LAST_SHIFT              13
#define BCHP_MEMC_GEN_0_SEQ_CMD_DBG_4_CAS0_LAST_DEFAULT            0

/* MEMC_GEN_0 :: SEQ_CMD_DBG_4 :: CAS0_AP [12:12] */
#define BCHP_MEMC_GEN_0_SEQ_CMD_DBG_4_CAS0_AP_MASK                 0x00001000
#define BCHP_MEMC_GEN_0_SEQ_CMD_DBG_4_CAS0_AP_SHIFT                12
#define BCHP_MEMC_GEN_0_SEQ_CMD_DBG_4_CAS0_AP_DEFAULT              0

/* MEMC_GEN_0 :: SEQ_CMD_DBG_4 :: CAS0_BANK_ADDR [11:09] */
#define BCHP_MEMC_GEN_0_SEQ_CMD_DBG_4_CAS0_BANK_ADDR_MASK          0x00000e00
#define BCHP_MEMC_GEN_0_SEQ_CMD_DBG_4_CAS0_BANK_ADDR_SHIFT         9
#define BCHP_MEMC_GEN_0_SEQ_CMD_DBG_4_CAS0_BANK_ADDR_DEFAULT       0

/* MEMC_GEN_0 :: SEQ_CMD_DBG_4 :: CAS0_POSITION [08:07] */
#define BCHP_MEMC_GEN_0_SEQ_CMD_DBG_4_CAS0_POSITION_MASK           0x00000180
#define BCHP_MEMC_GEN_0_SEQ_CMD_DBG_4_CAS0_POSITION_SHIFT          7
#define BCHP_MEMC_GEN_0_SEQ_CMD_DBG_4_CAS0_POSITION_DEFAULT        0

/* MEMC_GEN_0 :: SEQ_CMD_DBG_4 :: CAS0_ISSUED [06:06] */
#define BCHP_MEMC_GEN_0_SEQ_CMD_DBG_4_CAS0_ISSUED_MASK             0x00000040
#define BCHP_MEMC_GEN_0_SEQ_CMD_DBG_4_CAS0_ISSUED_SHIFT            6
#define BCHP_MEMC_GEN_0_SEQ_CMD_DBG_4_CAS0_ISSUED_DEFAULT          0

/* MEMC_GEN_0 :: SEQ_CMD_DBG_4 :: RAS_BANK_ADDR [05:03] */
#define BCHP_MEMC_GEN_0_SEQ_CMD_DBG_4_RAS_BANK_ADDR_MASK           0x00000038
#define BCHP_MEMC_GEN_0_SEQ_CMD_DBG_4_RAS_BANK_ADDR_SHIFT          3
#define BCHP_MEMC_GEN_0_SEQ_CMD_DBG_4_RAS_BANK_ADDR_DEFAULT        0

/* MEMC_GEN_0 :: SEQ_CMD_DBG_4 :: RAS_POSITION [02:01] */
#define BCHP_MEMC_GEN_0_SEQ_CMD_DBG_4_RAS_POSITION_MASK            0x00000006
#define BCHP_MEMC_GEN_0_SEQ_CMD_DBG_4_RAS_POSITION_SHIFT           1
#define BCHP_MEMC_GEN_0_SEQ_CMD_DBG_4_RAS_POSITION_DEFAULT         0

/* MEMC_GEN_0 :: SEQ_CMD_DBG_4 :: RAS_ISSUED [00:00] */
#define BCHP_MEMC_GEN_0_SEQ_CMD_DBG_4_RAS_ISSUED_MASK              0x00000001
#define BCHP_MEMC_GEN_0_SEQ_CMD_DBG_4_RAS_ISSUED_SHIFT             0
#define BCHP_MEMC_GEN_0_SEQ_CMD_DBG_4_RAS_ISSUED_DEFAULT           0

/***************************************************************************
 *SEQ_INPUT_DBG_INFO - Current input from CMD formatter to seq.
 ***************************************************************************/
/* MEMC_GEN_0 :: SEQ_INPUT_DBG_INFO :: reserved0 [31:17] */
#define BCHP_MEMC_GEN_0_SEQ_INPUT_DBG_INFO_reserved0_MASK          0xfffe0000
#define BCHP_MEMC_GEN_0_SEQ_INPUT_DBG_INFO_reserved0_SHIFT         17

/* MEMC_GEN_0 :: SEQ_INPUT_DBG_INFO :: CAS_1_LAST [16:16] */
#define BCHP_MEMC_GEN_0_SEQ_INPUT_DBG_INFO_CAS_1_LAST_MASK         0x00010000
#define BCHP_MEMC_GEN_0_SEQ_INPUT_DBG_INFO_CAS_1_LAST_SHIFT        16
#define BCHP_MEMC_GEN_0_SEQ_INPUT_DBG_INFO_CAS_1_LAST_DEFAULT      0

/* MEMC_GEN_0 :: SEQ_INPUT_DBG_INFO :: CAS_1_AP [15:15] */
#define BCHP_MEMC_GEN_0_SEQ_INPUT_DBG_INFO_CAS_1_AP_MASK           0x00008000
#define BCHP_MEMC_GEN_0_SEQ_INPUT_DBG_INFO_CAS_1_AP_SHIFT          15
#define BCHP_MEMC_GEN_0_SEQ_INPUT_DBG_INFO_CAS_1_AP_DEFAULT        0

/* MEMC_GEN_0 :: SEQ_INPUT_DBG_INFO :: CAS_1_BANK_ADDR [14:12] */
#define BCHP_MEMC_GEN_0_SEQ_INPUT_DBG_INFO_CAS_1_BANK_ADDR_MASK    0x00007000
#define BCHP_MEMC_GEN_0_SEQ_INPUT_DBG_INFO_CAS_1_BANK_ADDR_SHIFT   12
#define BCHP_MEMC_GEN_0_SEQ_INPUT_DBG_INFO_CAS_1_BANK_ADDR_DEFAULT 0

/* MEMC_GEN_0 :: SEQ_INPUT_DBG_INFO :: CAS_1_VALID [11:11] */
#define BCHP_MEMC_GEN_0_SEQ_INPUT_DBG_INFO_CAS_1_VALID_MASK        0x00000800
#define BCHP_MEMC_GEN_0_SEQ_INPUT_DBG_INFO_CAS_1_VALID_SHIFT       11
#define BCHP_MEMC_GEN_0_SEQ_INPUT_DBG_INFO_CAS_1_VALID_DEFAULT     0

/* MEMC_GEN_0 :: SEQ_INPUT_DBG_INFO :: CAS_0_LAST [10:10] */
#define BCHP_MEMC_GEN_0_SEQ_INPUT_DBG_INFO_CAS_0_LAST_MASK         0x00000400
#define BCHP_MEMC_GEN_0_SEQ_INPUT_DBG_INFO_CAS_0_LAST_SHIFT        10
#define BCHP_MEMC_GEN_0_SEQ_INPUT_DBG_INFO_CAS_0_LAST_DEFAULT      0

/* MEMC_GEN_0 :: SEQ_INPUT_DBG_INFO :: CAS_0_AP [09:09] */
#define BCHP_MEMC_GEN_0_SEQ_INPUT_DBG_INFO_CAS_0_AP_MASK           0x00000200
#define BCHP_MEMC_GEN_0_SEQ_INPUT_DBG_INFO_CAS_0_AP_SHIFT          9
#define BCHP_MEMC_GEN_0_SEQ_INPUT_DBG_INFO_CAS_0_AP_DEFAULT        0

/* MEMC_GEN_0 :: SEQ_INPUT_DBG_INFO :: CAS_0_BANK_ADDR [08:06] */
#define BCHP_MEMC_GEN_0_SEQ_INPUT_DBG_INFO_CAS_0_BANK_ADDR_MASK    0x000001c0
#define BCHP_MEMC_GEN_0_SEQ_INPUT_DBG_INFO_CAS_0_BANK_ADDR_SHIFT   6
#define BCHP_MEMC_GEN_0_SEQ_INPUT_DBG_INFO_CAS_0_BANK_ADDR_DEFAULT 0

/* MEMC_GEN_0 :: SEQ_INPUT_DBG_INFO :: CAS_0_VALID [05:05] */
#define BCHP_MEMC_GEN_0_SEQ_INPUT_DBG_INFO_CAS_0_VALID_MASK        0x00000020
#define BCHP_MEMC_GEN_0_SEQ_INPUT_DBG_INFO_CAS_0_VALID_SHIFT       5
#define BCHP_MEMC_GEN_0_SEQ_INPUT_DBG_INFO_CAS_0_VALID_DEFAULT     0

/* MEMC_GEN_0 :: SEQ_INPUT_DBG_INFO :: RAS_BANK_ADDR [04:02] */
#define BCHP_MEMC_GEN_0_SEQ_INPUT_DBG_INFO_RAS_BANK_ADDR_MASK      0x0000001c
#define BCHP_MEMC_GEN_0_SEQ_INPUT_DBG_INFO_RAS_BANK_ADDR_SHIFT     2
#define BCHP_MEMC_GEN_0_SEQ_INPUT_DBG_INFO_RAS_BANK_ADDR_DEFAULT   0

/* MEMC_GEN_0 :: SEQ_INPUT_DBG_INFO :: RAS_CMD_DATA [01:01] */
#define BCHP_MEMC_GEN_0_SEQ_INPUT_DBG_INFO_RAS_CMD_DATA_MASK       0x00000002
#define BCHP_MEMC_GEN_0_SEQ_INPUT_DBG_INFO_RAS_CMD_DATA_SHIFT      1
#define BCHP_MEMC_GEN_0_SEQ_INPUT_DBG_INFO_RAS_CMD_DATA_DEFAULT    0

/* MEMC_GEN_0 :: SEQ_INPUT_DBG_INFO :: RAS_CMD_RDY [00:00] */
#define BCHP_MEMC_GEN_0_SEQ_INPUT_DBG_INFO_RAS_CMD_RDY_MASK        0x00000001
#define BCHP_MEMC_GEN_0_SEQ_INPUT_DBG_INFO_RAS_CMD_RDY_SHIFT       0
#define BCHP_MEMC_GEN_0_SEQ_INPUT_DBG_INFO_RAS_CMD_RDY_DEFAULT     0

/***************************************************************************
 *MISC_SEQ_DBG_INFO - Status register of MISC command Sequencer.
 ***************************************************************************/
/* MEMC_GEN_0 :: MISC_SEQ_DBG_INFO :: reserved0 [31:21] */
#define BCHP_MEMC_GEN_0_MISC_SEQ_DBG_INFO_reserved0_MASK           0xffe00000
#define BCHP_MEMC_GEN_0_MISC_SEQ_DBG_INFO_reserved0_SHIFT          21

/* MEMC_GEN_0 :: MISC_SEQ_DBG_INFO :: INIT_DONE [20:20] */
#define BCHP_MEMC_GEN_0_MISC_SEQ_DBG_INFO_INIT_DONE_MASK           0x00100000
#define BCHP_MEMC_GEN_0_MISC_SEQ_DBG_INFO_INIT_DONE_SHIFT          20
#define BCHP_MEMC_GEN_0_MISC_SEQ_DBG_INFO_INIT_DONE_DEFAULT        0

/* MEMC_GEN_0 :: MISC_SEQ_DBG_INFO :: ILLEGAL_CMD_COUNT [19:16] */
#define BCHP_MEMC_GEN_0_MISC_SEQ_DBG_INFO_ILLEGAL_CMD_COUNT_MASK   0x000f0000
#define BCHP_MEMC_GEN_0_MISC_SEQ_DBG_INFO_ILLEGAL_CMD_COUNT_SHIFT  16
#define BCHP_MEMC_GEN_0_MISC_SEQ_DBG_INFO_ILLEGAL_CMD_COUNT_DEFAULT 0

/* MEMC_GEN_0 :: MISC_SEQ_DBG_INFO :: LAST_ILLEGAL_CMD [15:11] */
#define BCHP_MEMC_GEN_0_MISC_SEQ_DBG_INFO_LAST_ILLEGAL_CMD_MASK    0x0000f800
#define BCHP_MEMC_GEN_0_MISC_SEQ_DBG_INFO_LAST_ILLEGAL_CMD_SHIFT   11
#define BCHP_MEMC_GEN_0_MISC_SEQ_DBG_INFO_LAST_ILLEGAL_CMD_DEFAULT 0

/* MEMC_GEN_0 :: MISC_SEQ_DBG_INFO :: CURRENT_STATE [10:09] */
#define BCHP_MEMC_GEN_0_MISC_SEQ_DBG_INFO_CURRENT_STATE_MASK       0x00000600
#define BCHP_MEMC_GEN_0_MISC_SEQ_DBG_INFO_CURRENT_STATE_SHIFT      9
#define BCHP_MEMC_GEN_0_MISC_SEQ_DBG_INFO_CURRENT_STATE_DEFAULT    0

/* MEMC_GEN_0 :: MISC_SEQ_DBG_INFO :: INPUT_CMD_CODE [08:00] */
#define BCHP_MEMC_GEN_0_MISC_SEQ_DBG_INFO_INPUT_CMD_CODE_MASK      0x000001ff
#define BCHP_MEMC_GEN_0_MISC_SEQ_DBG_INFO_INPUT_CMD_CODE_SHIFT     0
#define BCHP_MEMC_GEN_0_MISC_SEQ_DBG_INFO_INPUT_CMD_CODE_DEFAULT   0

/***************************************************************************
 *BIU_DBG_INFO - Debug information from BIU>
 ***************************************************************************/
/* MEMC_GEN_0 :: BIU_DBG_INFO :: BIU_DBG_INFO [31:00] */
#define BCHP_MEMC_GEN_0_BIU_DBG_INFO_BIU_DBG_INFO_MASK             0xffffffff
#define BCHP_MEMC_GEN_0_BIU_DBG_INFO_BIU_DBG_INFO_SHIFT            0
#define BCHP_MEMC_GEN_0_BIU_DBG_INFO_BIU_DBG_INFO_DEFAULT          0

/***************************************************************************
 *SPARE_RO_3 - Start Address corresponding to SCB command that occurred three commands earlier or end addr in case of PFRI.
 ***************************************************************************/
/* MEMC_GEN_0 :: SPARE_RO_3 :: SPARE_RO [31:00] */
#define BCHP_MEMC_GEN_0_SPARE_RO_3_SPARE_RO_MASK                   0xffffffff
#define BCHP_MEMC_GEN_0_SPARE_RO_3_SPARE_RO_SHIFT                  0
#define BCHP_MEMC_GEN_0_SPARE_RO_3_SPARE_RO_DEFAULT                0

/***************************************************************************
 *TP_ADRS - Test Port Address Register
 ***************************************************************************/
/* MEMC_GEN_0 :: TP_ADRS :: reserved0 [31:05] */
#define BCHP_MEMC_GEN_0_TP_ADRS_reserved0_MASK                     0xffffffe0
#define BCHP_MEMC_GEN_0_TP_ADRS_reserved0_SHIFT                    5

/* MEMC_GEN_0 :: TP_ADRS :: SOFT_MODE [04:04] */
#define BCHP_MEMC_GEN_0_TP_ADRS_SOFT_MODE_MASK                     0x00000010
#define BCHP_MEMC_GEN_0_TP_ADRS_SOFT_MODE_SHIFT                    4
#define BCHP_MEMC_GEN_0_TP_ADRS_SOFT_MODE_DEFAULT                  0

/* MEMC_GEN_0 :: TP_ADRS :: reserved1 [03:03] */
#define BCHP_MEMC_GEN_0_TP_ADRS_reserved1_MASK                     0x00000008
#define BCHP_MEMC_GEN_0_TP_ADRS_reserved1_SHIFT                    3

/* MEMC_GEN_0 :: TP_ADRS :: ADRS [02:00] */
#define BCHP_MEMC_GEN_0_TP_ADRS_ADRS_MASK                          0x00000007
#define BCHP_MEMC_GEN_0_TP_ADRS_ADRS_SHIFT                         0
#define BCHP_MEMC_GEN_0_TP_ADRS_ADRS_DEFAULT                       0

/***************************************************************************
 *TP_READ_DATA - Test Port Data Read Register
 ***************************************************************************/
/* union - case SCB_CMD [31:00] */
/* MEMC_GEN_0 :: TP_READ_DATA :: SCB_CMD :: SCB_CMD [31:08] */
#define BCHP_MEMC_GEN_0_TP_READ_DATA_SCB_CMD_SCB_CMD_MASK          0xffffff00
#define BCHP_MEMC_GEN_0_TP_READ_DATA_SCB_CMD_SCB_CMD_SHIFT         8
#define BCHP_MEMC_GEN_0_TP_READ_DATA_SCB_CMD_SCB_CMD_DEFAULT       0

/* MEMC_GEN_0 :: TP_READ_DATA :: SCB_CMD :: CLIENT_ID [07:01] */
#define BCHP_MEMC_GEN_0_TP_READ_DATA_SCB_CMD_CLIENT_ID_MASK        0x000000fe
#define BCHP_MEMC_GEN_0_TP_READ_DATA_SCB_CMD_CLIENT_ID_SHIFT       1
#define BCHP_MEMC_GEN_0_TP_READ_DATA_SCB_CMD_CLIENT_ID_DEFAULT     0

/* MEMC_GEN_0 :: TP_READ_DATA :: SCB_CMD :: CMD_ACK [00:00] */
#define BCHP_MEMC_GEN_0_TP_READ_DATA_SCB_CMD_CMD_ACK_MASK          0x00000001
#define BCHP_MEMC_GEN_0_TP_READ_DATA_SCB_CMD_CMD_ACK_SHIFT         0
#define BCHP_MEMC_GEN_0_TP_READ_DATA_SCB_CMD_CMD_ACK_DEFAULT       0

/* union - case SCB_RD_DATA [31:00] */
/* MEMC_GEN_0 :: TP_READ_DATA :: SCB_RD_DATA :: RD_END_ACK [31:31] */
#define BCHP_MEMC_GEN_0_TP_READ_DATA_SCB_RD_DATA_RD_END_ACK_MASK   0x80000000
#define BCHP_MEMC_GEN_0_TP_READ_DATA_SCB_RD_DATA_RD_END_ACK_SHIFT  31
#define BCHP_MEMC_GEN_0_TP_READ_DATA_SCB_RD_DATA_RD_END_ACK_DEFAULT 0

/* MEMC_GEN_0 :: TP_READ_DATA :: SCB_RD_DATA :: RD_STRB [30:30] */
#define BCHP_MEMC_GEN_0_TP_READ_DATA_SCB_RD_DATA_RD_STRB_MASK      0x40000000
#define BCHP_MEMC_GEN_0_TP_READ_DATA_SCB_RD_DATA_RD_STRB_SHIFT     30
#define BCHP_MEMC_GEN_0_TP_READ_DATA_SCB_RD_DATA_RD_STRB_DEFAULT   0

/* MEMC_GEN_0 :: TP_READ_DATA :: SCB_RD_DATA :: CLIENT_ID [29:24] */
#define BCHP_MEMC_GEN_0_TP_READ_DATA_SCB_RD_DATA_CLIENT_ID_MASK    0x3f000000
#define BCHP_MEMC_GEN_0_TP_READ_DATA_SCB_RD_DATA_CLIENT_ID_SHIFT   24
#define BCHP_MEMC_GEN_0_TP_READ_DATA_SCB_RD_DATA_CLIENT_ID_DEFAULT 0

/* MEMC_GEN_0 :: TP_READ_DATA :: SCB_RD_DATA :: SCB_RD_DATA [23:00] */
#define BCHP_MEMC_GEN_0_TP_READ_DATA_SCB_RD_DATA_SCB_RD_DATA_MASK  0x00ffffff
#define BCHP_MEMC_GEN_0_TP_READ_DATA_SCB_RD_DATA_SCB_RD_DATA_SHIFT 0
#define BCHP_MEMC_GEN_0_TP_READ_DATA_SCB_RD_DATA_SCB_RD_DATA_DEFAULT 0

/* union - case SCB_WR_DATA [31:00] */
/* MEMC_GEN_0 :: TP_READ_DATA :: SCB_WR_DATA :: WR_END_ACK [31:31] */
#define BCHP_MEMC_GEN_0_TP_READ_DATA_SCB_WR_DATA_WR_END_ACK_MASK   0x80000000
#define BCHP_MEMC_GEN_0_TP_READ_DATA_SCB_WR_DATA_WR_END_ACK_SHIFT  31
#define BCHP_MEMC_GEN_0_TP_READ_DATA_SCB_WR_DATA_WR_END_ACK_DEFAULT 0

/* MEMC_GEN_0 :: TP_READ_DATA :: SCB_WR_DATA :: WR_STRB [30:30] */
#define BCHP_MEMC_GEN_0_TP_READ_DATA_SCB_WR_DATA_WR_STRB_MASK      0x40000000
#define BCHP_MEMC_GEN_0_TP_READ_DATA_SCB_WR_DATA_WR_STRB_SHIFT     30
#define BCHP_MEMC_GEN_0_TP_READ_DATA_SCB_WR_DATA_WR_STRB_DEFAULT   0

/* MEMC_GEN_0 :: TP_READ_DATA :: SCB_WR_DATA :: CLIENT_ID [29:24] */
#define BCHP_MEMC_GEN_0_TP_READ_DATA_SCB_WR_DATA_CLIENT_ID_MASK    0x3f000000
#define BCHP_MEMC_GEN_0_TP_READ_DATA_SCB_WR_DATA_CLIENT_ID_SHIFT   24
#define BCHP_MEMC_GEN_0_TP_READ_DATA_SCB_WR_DATA_CLIENT_ID_DEFAULT 0

/* MEMC_GEN_0 :: TP_READ_DATA :: SCB_WR_DATA :: SCB_WR_DATA [23:00] */
#define BCHP_MEMC_GEN_0_TP_READ_DATA_SCB_WR_DATA_SCB_WR_DATA_MASK  0x00ffffff
#define BCHP_MEMC_GEN_0_TP_READ_DATA_SCB_WR_DATA_SCB_WR_DATA_SHIFT 0
#define BCHP_MEMC_GEN_0_TP_READ_DATA_SCB_WR_DATA_SCB_WR_DATA_DEFAULT 0

/* union - case PRED_SIGNALS [31:00] */
/* MEMC_GEN_0 :: TP_READ_DATA :: PRED_SIGNALS :: reserved0 [31:30] */
#define BCHP_MEMC_GEN_0_TP_READ_DATA_PRED_SIGNALS_reserved0_MASK   0xc0000000
#define BCHP_MEMC_GEN_0_TP_READ_DATA_PRED_SIGNALS_reserved0_SHIFT  30

/* MEMC_GEN_0 :: TP_READ_DATA :: PRED_SIGNALS :: lin_rdcmd [29:29] */
#define BCHP_MEMC_GEN_0_TP_READ_DATA_PRED_SIGNALS_lin_rdcmd_MASK   0x20000000
#define BCHP_MEMC_GEN_0_TP_READ_DATA_PRED_SIGNALS_lin_rdcmd_SHIFT  29
#define BCHP_MEMC_GEN_0_TP_READ_DATA_PRED_SIGNALS_lin_rdcmd_DEFAULT 0

/* MEMC_GEN_0 :: TP_READ_DATA :: PRED_SIGNALS :: lin_wrcmd [28:28] */
#define BCHP_MEMC_GEN_0_TP_READ_DATA_PRED_SIGNALS_lin_wrcmd_MASK   0x10000000
#define BCHP_MEMC_GEN_0_TP_READ_DATA_PRED_SIGNALS_lin_wrcmd_SHIFT  28
#define BCHP_MEMC_GEN_0_TP_READ_DATA_PRED_SIGNALS_lin_wrcmd_DEFAULT 0

/* MEMC_GEN_0 :: TP_READ_DATA :: PRED_SIGNALS :: dis_rdcmd [27:27] */
#define BCHP_MEMC_GEN_0_TP_READ_DATA_PRED_SIGNALS_dis_rdcmd_MASK   0x08000000
#define BCHP_MEMC_GEN_0_TP_READ_DATA_PRED_SIGNALS_dis_rdcmd_SHIFT  27
#define BCHP_MEMC_GEN_0_TP_READ_DATA_PRED_SIGNALS_dis_rdcmd_DEFAULT 0

/* MEMC_GEN_0 :: TP_READ_DATA :: PRED_SIGNALS :: refcmd [26:26] */
#define BCHP_MEMC_GEN_0_TP_READ_DATA_PRED_SIGNALS_refcmd_MASK      0x04000000
#define BCHP_MEMC_GEN_0_TP_READ_DATA_PRED_SIGNALS_refcmd_SHIFT     26
#define BCHP_MEMC_GEN_0_TP_READ_DATA_PRED_SIGNALS_refcmd_DEFAULT   0

/* MEMC_GEN_0 :: TP_READ_DATA :: PRED_SIGNALS :: mrscmd [25:25] */
#define BCHP_MEMC_GEN_0_TP_READ_DATA_PRED_SIGNALS_mrscmd_MASK      0x02000000
#define BCHP_MEMC_GEN_0_TP_READ_DATA_PRED_SIGNALS_mrscmd_SHIFT     25
#define BCHP_MEMC_GEN_0_TP_READ_DATA_PRED_SIGNALS_mrscmd_DEFAULT   0

/* MEMC_GEN_0 :: TP_READ_DATA :: PRED_SIGNALS :: emrscmd [24:24] */
#define BCHP_MEMC_GEN_0_TP_READ_DATA_PRED_SIGNALS_emrscmd_MASK     0x01000000
#define BCHP_MEMC_GEN_0_TP_READ_DATA_PRED_SIGNALS_emrscmd_SHIFT    24
#define BCHP_MEMC_GEN_0_TP_READ_DATA_PRED_SIGNALS_emrscmd_DEFAULT  0

/* MEMC_GEN_0 :: TP_READ_DATA :: PRED_SIGNALS :: pallcmd [23:23] */
#define BCHP_MEMC_GEN_0_TP_READ_DATA_PRED_SIGNALS_pallcmd_MASK     0x00800000
#define BCHP_MEMC_GEN_0_TP_READ_DATA_PRED_SIGNALS_pallcmd_SHIFT    23
#define BCHP_MEMC_GEN_0_TP_READ_DATA_PRED_SIGNALS_pallcmd_DEFAULT  0

/* MEMC_GEN_0 :: TP_READ_DATA :: PRED_SIGNALS :: recon_16pix_wrcmd [22:22] */
#define BCHP_MEMC_GEN_0_TP_READ_DATA_PRED_SIGNALS_recon_16pix_wrcmd_MASK 0x00400000
#define BCHP_MEMC_GEN_0_TP_READ_DATA_PRED_SIGNALS_recon_16pix_wrcmd_SHIFT 22
#define BCHP_MEMC_GEN_0_TP_READ_DATA_PRED_SIGNALS_recon_16pix_wrcmd_DEFAULT 0

/* MEMC_GEN_0 :: TP_READ_DATA :: PRED_SIGNALS :: mpeg_field_pic [21:21] */
#define BCHP_MEMC_GEN_0_TP_READ_DATA_PRED_SIGNALS_mpeg_field_pic_MASK 0x00200000
#define BCHP_MEMC_GEN_0_TP_READ_DATA_PRED_SIGNALS_mpeg_field_pic_SHIFT 21
#define BCHP_MEMC_GEN_0_TP_READ_DATA_PRED_SIGNALS_mpeg_field_pic_DEFAULT 0

/* MEMC_GEN_0 :: TP_READ_DATA :: PRED_SIGNALS :: invalid_cmd [20:20] */
#define BCHP_MEMC_GEN_0_TP_READ_DATA_PRED_SIGNALS_invalid_cmd_MASK 0x00100000
#define BCHP_MEMC_GEN_0_TP_READ_DATA_PRED_SIGNALS_invalid_cmd_SHIFT 20
#define BCHP_MEMC_GEN_0_TP_READ_DATA_PRED_SIGNALS_invalid_cmd_DEFAULT 0

/* MEMC_GEN_0 :: TP_READ_DATA :: PRED_SIGNALS :: strobable_wrcmd [19:19] */
#define BCHP_MEMC_GEN_0_TP_READ_DATA_PRED_SIGNALS_strobable_wrcmd_MASK 0x00080000
#define BCHP_MEMC_GEN_0_TP_READ_DATA_PRED_SIGNALS_strobable_wrcmd_SHIFT 19
#define BCHP_MEMC_GEN_0_TP_READ_DATA_PRED_SIGNALS_strobable_wrcmd_DEFAULT 0

/* MEMC_GEN_0 :: TP_READ_DATA :: PRED_SIGNALS :: strobable_rdcmd [18:18] */
#define BCHP_MEMC_GEN_0_TP_READ_DATA_PRED_SIGNALS_strobable_rdcmd_MASK 0x00040000
#define BCHP_MEMC_GEN_0_TP_READ_DATA_PRED_SIGNALS_strobable_rdcmd_SHIFT 18
#define BCHP_MEMC_GEN_0_TP_READ_DATA_PRED_SIGNALS_strobable_rdcmd_DEFAULT 0

/* MEMC_GEN_0 :: TP_READ_DATA :: PRED_SIGNALS :: mpeg_ver3_strad [17:17] */
#define BCHP_MEMC_GEN_0_TP_READ_DATA_PRED_SIGNALS_mpeg_ver3_strad_MASK 0x00020000
#define BCHP_MEMC_GEN_0_TP_READ_DATA_PRED_SIGNALS_mpeg_ver3_strad_SHIFT 17
#define BCHP_MEMC_GEN_0_TP_READ_DATA_PRED_SIGNALS_mpeg_ver3_strad_DEFAULT 0

/* MEMC_GEN_0 :: TP_READ_DATA :: PRED_SIGNALS :: mpeg_ver2_strad [16:16] */
#define BCHP_MEMC_GEN_0_TP_READ_DATA_PRED_SIGNALS_mpeg_ver2_strad_MASK 0x00010000
#define BCHP_MEMC_GEN_0_TP_READ_DATA_PRED_SIGNALS_mpeg_ver2_strad_SHIFT 16
#define BCHP_MEMC_GEN_0_TP_READ_DATA_PRED_SIGNALS_mpeg_ver2_strad_DEFAULT 0

/* MEMC_GEN_0 :: TP_READ_DATA :: PRED_SIGNALS :: mpeg_ver1_strad [15:15] */
#define BCHP_MEMC_GEN_0_TP_READ_DATA_PRED_SIGNALS_mpeg_ver1_strad_MASK 0x00008000
#define BCHP_MEMC_GEN_0_TP_READ_DATA_PRED_SIGNALS_mpeg_ver1_strad_SHIFT 15
#define BCHP_MEMC_GEN_0_TP_READ_DATA_PRED_SIGNALS_mpeg_ver1_strad_DEFAULT 0

/* MEMC_GEN_0 :: TP_READ_DATA :: PRED_SIGNALS :: mpeg_adj_strad [14:14] */
#define BCHP_MEMC_GEN_0_TP_READ_DATA_PRED_SIGNALS_mpeg_adj_strad_MASK 0x00004000
#define BCHP_MEMC_GEN_0_TP_READ_DATA_PRED_SIGNALS_mpeg_adj_strad_SHIFT 14
#define BCHP_MEMC_GEN_0_TP_READ_DATA_PRED_SIGNALS_mpeg_adj_strad_DEFAULT 0

/* MEMC_GEN_0 :: TP_READ_DATA :: PRED_SIGNALS :: dis_adj1_strad [13:13] */
#define BCHP_MEMC_GEN_0_TP_READ_DATA_PRED_SIGNALS_dis_adj1_strad_MASK 0x00002000
#define BCHP_MEMC_GEN_0_TP_READ_DATA_PRED_SIGNALS_dis_adj1_strad_SHIFT 13
#define BCHP_MEMC_GEN_0_TP_READ_DATA_PRED_SIGNALS_dis_adj1_strad_DEFAULT 0

/* MEMC_GEN_0 :: TP_READ_DATA :: PRED_SIGNALS :: dis_adj2_strad [12:12] */
#define BCHP_MEMC_GEN_0_TP_READ_DATA_PRED_SIGNALS_dis_adj2_strad_MASK 0x00001000
#define BCHP_MEMC_GEN_0_TP_READ_DATA_PRED_SIGNALS_dis_adj2_strad_SHIFT 12
#define BCHP_MEMC_GEN_0_TP_READ_DATA_PRED_SIGNALS_dis_adj2_strad_DEFAULT 0

/* MEMC_GEN_0 :: TP_READ_DATA :: PRED_SIGNALS :: dis_adj3_strad [11:11] */
#define BCHP_MEMC_GEN_0_TP_READ_DATA_PRED_SIGNALS_dis_adj3_strad_MASK 0x00000800
#define BCHP_MEMC_GEN_0_TP_READ_DATA_PRED_SIGNALS_dis_adj3_strad_SHIFT 11
#define BCHP_MEMC_GEN_0_TP_READ_DATA_PRED_SIGNALS_dis_adj3_strad_DEFAULT 0

/* MEMC_GEN_0 :: TP_READ_DATA :: PRED_SIGNALS :: dis_adj4_strad [10:10] */
#define BCHP_MEMC_GEN_0_TP_READ_DATA_PRED_SIGNALS_dis_adj4_strad_MASK 0x00000400
#define BCHP_MEMC_GEN_0_TP_READ_DATA_PRED_SIGNALS_dis_adj4_strad_SHIFT 10
#define BCHP_MEMC_GEN_0_TP_READ_DATA_PRED_SIGNALS_dis_adj4_strad_DEFAULT 0

/* MEMC_GEN_0 :: TP_READ_DATA :: PRED_SIGNALS :: lin_adj_strad [09:09] */
#define BCHP_MEMC_GEN_0_TP_READ_DATA_PRED_SIGNALS_lin_adj_strad_MASK 0x00000200
#define BCHP_MEMC_GEN_0_TP_READ_DATA_PRED_SIGNALS_lin_adj_strad_SHIFT 9
#define BCHP_MEMC_GEN_0_TP_READ_DATA_PRED_SIGNALS_lin_adj_strad_DEFAULT 0

/* MEMC_GEN_0 :: TP_READ_DATA :: PRED_SIGNALS :: n_nativewrds [08:00] */
#define BCHP_MEMC_GEN_0_TP_READ_DATA_PRED_SIGNALS_n_nativewrds_MASK 0x000001ff
#define BCHP_MEMC_GEN_0_TP_READ_DATA_PRED_SIGNALS_n_nativewrds_SHIFT 0
#define BCHP_MEMC_GEN_0_TP_READ_DATA_PRED_SIGNALS_n_nativewrds_DEFAULT 0

/* union - case CMD_END_ADRS [31:00] */
/* MEMC_GEN_0 :: TP_READ_DATA :: CMD_END_ADRS :: reserved0 [31:29] */
#define BCHP_MEMC_GEN_0_TP_READ_DATA_CMD_END_ADRS_reserved0_MASK   0xe0000000
#define BCHP_MEMC_GEN_0_TP_READ_DATA_CMD_END_ADRS_reserved0_SHIFT  29

/* MEMC_GEN_0 :: TP_READ_DATA :: CMD_END_ADRS :: END_ADRS [28:00] */
#define BCHP_MEMC_GEN_0_TP_READ_DATA_CMD_END_ADRS_END_ADRS_MASK    0x1fffffff
#define BCHP_MEMC_GEN_0_TP_READ_DATA_CMD_END_ADRS_END_ADRS_SHIFT   0
#define BCHP_MEMC_GEN_0_TP_READ_DATA_CMD_END_ADRS_END_ADRS_DEFAULT 0

/* union - case SEQ_SM [31:00] */
/* MEMC_GEN_0 :: TP_READ_DATA :: SEQ_SM :: reserved0 [31:06] */
#define BCHP_MEMC_GEN_0_TP_READ_DATA_SEQ_SM_reserved0_MASK         0xffffffc0
#define BCHP_MEMC_GEN_0_TP_READ_DATA_SEQ_SM_reserved0_SHIFT        6

/* MEMC_GEN_0 :: TP_READ_DATA :: SEQ_SM :: SM_VAL [05:00] */
#define BCHP_MEMC_GEN_0_TP_READ_DATA_SEQ_SM_SM_VAL_MASK            0x0000003f
#define BCHP_MEMC_GEN_0_TP_READ_DATA_SEQ_SM_SM_VAL_SHIFT           0
#define BCHP_MEMC_GEN_0_TP_READ_DATA_SEQ_SM_SM_VAL_DEFAULT         0

/***************************************************************************
 *ARC_0_CNTRL - Mode/Control register for Address Range Checker (ARC)-0
 ***************************************************************************/
/* MEMC_GEN_0 :: ARC_0_CNTRL :: reserved0 [31:05] */
#define BCHP_MEMC_GEN_0_ARC_0_CNTRL_reserved0_MASK                 0xffffffe0
#define BCHP_MEMC_GEN_0_ARC_0_CNTRL_reserved0_SHIFT                5

/* MEMC_GEN_0 :: ARC_0_CNTRL :: WRITE_CMD_ABORT [04:04] */
#define BCHP_MEMC_GEN_0_ARC_0_CNTRL_WRITE_CMD_ABORT_MASK           0x00000010
#define BCHP_MEMC_GEN_0_ARC_0_CNTRL_WRITE_CMD_ABORT_SHIFT          4
#define BCHP_MEMC_GEN_0_ARC_0_CNTRL_WRITE_CMD_ABORT_DEFAULT        0
#define BCHP_MEMC_GEN_0_ARC_0_CNTRL_WRITE_CMD_ABORT_DISABLED       0
#define BCHP_MEMC_GEN_0_ARC_0_CNTRL_WRITE_CMD_ABORT_ENABLED        1

/* MEMC_GEN_0 :: ARC_0_CNTRL :: WRITE_CHECK [03:03] */
#define BCHP_MEMC_GEN_0_ARC_0_CNTRL_WRITE_CHECK_MASK               0x00000008
#define BCHP_MEMC_GEN_0_ARC_0_CNTRL_WRITE_CHECK_SHIFT              3
#define BCHP_MEMC_GEN_0_ARC_0_CNTRL_WRITE_CHECK_DEFAULT            0
#define BCHP_MEMC_GEN_0_ARC_0_CNTRL_WRITE_CHECK_DISABLED           0
#define BCHP_MEMC_GEN_0_ARC_0_CNTRL_WRITE_CHECK_ENABLED            1

/* MEMC_GEN_0 :: ARC_0_CNTRL :: READ_CMD_ABORT [02:02] */
#define BCHP_MEMC_GEN_0_ARC_0_CNTRL_READ_CMD_ABORT_MASK            0x00000004
#define BCHP_MEMC_GEN_0_ARC_0_CNTRL_READ_CMD_ABORT_SHIFT           2
#define BCHP_MEMC_GEN_0_ARC_0_CNTRL_READ_CMD_ABORT_DEFAULT         0
#define BCHP_MEMC_GEN_0_ARC_0_CNTRL_READ_CMD_ABORT_DISABLED        0
#define BCHP_MEMC_GEN_0_ARC_0_CNTRL_READ_CMD_ABORT_ENABLED         1

/* MEMC_GEN_0 :: ARC_0_CNTRL :: READ_CHECK [01:01] */
#define BCHP_MEMC_GEN_0_ARC_0_CNTRL_READ_CHECK_MASK                0x00000002
#define BCHP_MEMC_GEN_0_ARC_0_CNTRL_READ_CHECK_SHIFT               1
#define BCHP_MEMC_GEN_0_ARC_0_CNTRL_READ_CHECK_DEFAULT             0
#define BCHP_MEMC_GEN_0_ARC_0_CNTRL_READ_CHECK_DISABLED            0
#define BCHP_MEMC_GEN_0_ARC_0_CNTRL_READ_CHECK_ENABLED             1

/* MEMC_GEN_0 :: ARC_0_CNTRL :: MODE [00:00] */
#define BCHP_MEMC_GEN_0_ARC_0_CNTRL_MODE_MASK                      0x00000001
#define BCHP_MEMC_GEN_0_ARC_0_CNTRL_MODE_SHIFT                     0
#define BCHP_MEMC_GEN_0_ARC_0_CNTRL_MODE_DEFAULT                   0
#define BCHP_MEMC_GEN_0_ARC_0_CNTRL_MODE_NON_EXCLUSIVE             0
#define BCHP_MEMC_GEN_0_ARC_0_CNTRL_MODE_EXCLUSIVE                 1

/***************************************************************************
 *ARC_0_ADRS_RANGE_LOW - Lower Address of the memory range for Address Range Checker (ARC)-0.
 ***************************************************************************/
/* MEMC_GEN_0 :: ARC_0_ADRS_RANGE_LOW :: reserved0 [31:29] */
#define BCHP_MEMC_GEN_0_ARC_0_ADRS_RANGE_LOW_reserved0_MASK        0xe0000000
#define BCHP_MEMC_GEN_0_ARC_0_ADRS_RANGE_LOW_reserved0_SHIFT       29

/* MEMC_GEN_0 :: ARC_0_ADRS_RANGE_LOW :: ADDRESS [28:00] */
#define BCHP_MEMC_GEN_0_ARC_0_ADRS_RANGE_LOW_ADDRESS_MASK          0x1fffffff
#define BCHP_MEMC_GEN_0_ARC_0_ADRS_RANGE_LOW_ADDRESS_SHIFT         0
#define BCHP_MEMC_GEN_0_ARC_0_ADRS_RANGE_LOW_ADDRESS_DEFAULT       0

/***************************************************************************
 *ARC_0_ADRS_RANGE_HIGH - Higher Address of the memory range for Address Range Checker (ARC)-0.
 ***************************************************************************/
/* MEMC_GEN_0 :: ARC_0_ADRS_RANGE_HIGH :: reserved0 [31:29] */
#define BCHP_MEMC_GEN_0_ARC_0_ADRS_RANGE_HIGH_reserved0_MASK       0xe0000000
#define BCHP_MEMC_GEN_0_ARC_0_ADRS_RANGE_HIGH_reserved0_SHIFT      29

/* MEMC_GEN_0 :: ARC_0_ADRS_RANGE_HIGH :: ADDRESS [28:00] */
#define BCHP_MEMC_GEN_0_ARC_0_ADRS_RANGE_HIGH_ADDRESS_MASK         0x1fffffff
#define BCHP_MEMC_GEN_0_ARC_0_ADRS_RANGE_HIGH_ADDRESS_SHIFT        0
#define BCHP_MEMC_GEN_0_ARC_0_ADRS_RANGE_HIGH_ADDRESS_DEFAULT      0

/***************************************************************************
 *ARC_0_READ_RIGHTS_0 - Read access right of SCB clients 0 to 31 on Address Range Checker (ARC)-0
 ***************************************************************************/
/* MEMC_GEN_0 :: ARC_0_READ_RIGHTS_0 :: ACCESS_RIGHT [31:00] */
#define BCHP_MEMC_GEN_0_ARC_0_READ_RIGHTS_0_ACCESS_RIGHT_MASK      0xffffffff
#define BCHP_MEMC_GEN_0_ARC_0_READ_RIGHTS_0_ACCESS_RIGHT_SHIFT     0
#define BCHP_MEMC_GEN_0_ARC_0_READ_RIGHTS_0_ACCESS_RIGHT_DEFAULT   0

/***************************************************************************
 *ARC_0_READ_RIGHTS_1 - Read access right of SCB clients 32 to 63 on Address Range Checker(ARC)-0
 ***************************************************************************/
/* MEMC_GEN_0 :: ARC_0_READ_RIGHTS_1 :: ACCESS_RIGHT [31:00] */
#define BCHP_MEMC_GEN_0_ARC_0_READ_RIGHTS_1_ACCESS_RIGHT_MASK      0xffffffff
#define BCHP_MEMC_GEN_0_ARC_0_READ_RIGHTS_1_ACCESS_RIGHT_SHIFT     0
#define BCHP_MEMC_GEN_0_ARC_0_READ_RIGHTS_1_ACCESS_RIGHT_DEFAULT   0

/***************************************************************************
 *ARC_0_READ_RIGHTS_2 - Read access right of SCB clients 64 to 95 on Address Range Checker (ARC)-0
 ***************************************************************************/
/* MEMC_GEN_0 :: ARC_0_READ_RIGHTS_2 :: ACCESS_RIGHT [31:00] */
#define BCHP_MEMC_GEN_0_ARC_0_READ_RIGHTS_2_ACCESS_RIGHT_MASK      0xffffffff
#define BCHP_MEMC_GEN_0_ARC_0_READ_RIGHTS_2_ACCESS_RIGHT_SHIFT     0
#define BCHP_MEMC_GEN_0_ARC_0_READ_RIGHTS_2_ACCESS_RIGHT_DEFAULT   0

/***************************************************************************
 *ARC_0_READ_RIGHTS_3 - Read access right of SCB clients 96 to 127 on Address Range Checker(ARC)-0
 ***************************************************************************/
/* MEMC_GEN_0 :: ARC_0_READ_RIGHTS_3 :: ACCESS_RIGHT [31:00] */
#define BCHP_MEMC_GEN_0_ARC_0_READ_RIGHTS_3_ACCESS_RIGHT_MASK      0xffffffff
#define BCHP_MEMC_GEN_0_ARC_0_READ_RIGHTS_3_ACCESS_RIGHT_SHIFT     0
#define BCHP_MEMC_GEN_0_ARC_0_READ_RIGHTS_3_ACCESS_RIGHT_DEFAULT   0

/***************************************************************************
 *ARC_0_WRITE_RIGHTS_0 - Write access right of SCB clients 0 to 31 on Address Range Checker(ARC)-0
 ***************************************************************************/
/* MEMC_GEN_0 :: ARC_0_WRITE_RIGHTS_0 :: ACCESS_RIGHT [31:00] */
#define BCHP_MEMC_GEN_0_ARC_0_WRITE_RIGHTS_0_ACCESS_RIGHT_MASK     0xffffffff
#define BCHP_MEMC_GEN_0_ARC_0_WRITE_RIGHTS_0_ACCESS_RIGHT_SHIFT    0
#define BCHP_MEMC_GEN_0_ARC_0_WRITE_RIGHTS_0_ACCESS_RIGHT_DEFAULT  0

/***************************************************************************
 *ARC_0_WRITE_RIGHTS_1 - Write access right of SCB clients 32 to 63 on Address Range Checker(ARC)-0
 ***************************************************************************/
/* MEMC_GEN_0 :: ARC_0_WRITE_RIGHTS_1 :: ACCESS_RIGHT [31:00] */
#define BCHP_MEMC_GEN_0_ARC_0_WRITE_RIGHTS_1_ACCESS_RIGHT_MASK     0xffffffff
#define BCHP_MEMC_GEN_0_ARC_0_WRITE_RIGHTS_1_ACCESS_RIGHT_SHIFT    0
#define BCHP_MEMC_GEN_0_ARC_0_WRITE_RIGHTS_1_ACCESS_RIGHT_DEFAULT  0

/***************************************************************************
 *ARC_0_WRITE_RIGHTS_2 - Write access right of SCB clients 0 to 31 on Address Range Checker(ARC)-0
 ***************************************************************************/
/* MEMC_GEN_0 :: ARC_0_WRITE_RIGHTS_2 :: ACCESS_RIGHT [31:00] */
#define BCHP_MEMC_GEN_0_ARC_0_WRITE_RIGHTS_2_ACCESS_RIGHT_MASK     0xffffffff
#define BCHP_MEMC_GEN_0_ARC_0_WRITE_RIGHTS_2_ACCESS_RIGHT_SHIFT    0
#define BCHP_MEMC_GEN_0_ARC_0_WRITE_RIGHTS_2_ACCESS_RIGHT_DEFAULT  0

/***************************************************************************
 *ARC_0_WRITE_RIGHTS_3 - Write access right of SCB clients 32 to 63 on Address Range Checker(ARC)-0
 ***************************************************************************/
/* MEMC_GEN_0 :: ARC_0_WRITE_RIGHTS_3 :: ACCESS_RIGHT [31:00] */
#define BCHP_MEMC_GEN_0_ARC_0_WRITE_RIGHTS_3_ACCESS_RIGHT_MASK     0xffffffff
#define BCHP_MEMC_GEN_0_ARC_0_WRITE_RIGHTS_3_ACCESS_RIGHT_SHIFT    0
#define BCHP_MEMC_GEN_0_ARC_0_WRITE_RIGHTS_3_ACCESS_RIGHT_DEFAULT  0

/***************************************************************************
 *ARC_0_VIOLATION_INFO_START_ADDR - Violating Command Start Address for Address Range Checker (ARC)-0 .
 ***************************************************************************/
/* MEMC_GEN_0 :: ARC_0_VIOLATION_INFO_START_ADDR :: reserved0 [31:29] */
#define BCHP_MEMC_GEN_0_ARC_0_VIOLATION_INFO_START_ADDR_reserved0_MASK 0xe0000000
#define BCHP_MEMC_GEN_0_ARC_0_VIOLATION_INFO_START_ADDR_reserved0_SHIFT 29

/* MEMC_GEN_0 :: ARC_0_VIOLATION_INFO_START_ADDR :: ADDRESS [28:00] */
#define BCHP_MEMC_GEN_0_ARC_0_VIOLATION_INFO_START_ADDR_ADDRESS_MASK 0x1fffffff
#define BCHP_MEMC_GEN_0_ARC_0_VIOLATION_INFO_START_ADDR_ADDRESS_SHIFT 0
#define BCHP_MEMC_GEN_0_ARC_0_VIOLATION_INFO_START_ADDR_ADDRESS_DEFAULT 0

/***************************************************************************
 *ARC_0_VIOLATION_INFO_END_ADDR - Violating Command End Address for Address Range Checker (ARC)-0 .
 ***************************************************************************/
/* MEMC_GEN_0 :: ARC_0_VIOLATION_INFO_END_ADDR :: reserved0 [31:29] */
#define BCHP_MEMC_GEN_0_ARC_0_VIOLATION_INFO_END_ADDR_reserved0_MASK 0xe0000000
#define BCHP_MEMC_GEN_0_ARC_0_VIOLATION_INFO_END_ADDR_reserved0_SHIFT 29

/* MEMC_GEN_0 :: ARC_0_VIOLATION_INFO_END_ADDR :: ADDRESS [28:00] */
#define BCHP_MEMC_GEN_0_ARC_0_VIOLATION_INFO_END_ADDR_ADDRESS_MASK 0x1fffffff
#define BCHP_MEMC_GEN_0_ARC_0_VIOLATION_INFO_END_ADDR_ADDRESS_SHIFT 0
#define BCHP_MEMC_GEN_0_ARC_0_VIOLATION_INFO_END_ADDR_ADDRESS_DEFAULT 0

/***************************************************************************
 *ARC_0_VIOLATION_INFO_CMD - Violating SCB client-ID & Command Type for Address Range Checker (ARC)-0 .
 ***************************************************************************/
/* MEMC_GEN_0 :: ARC_0_VIOLATION_INFO_CMD :: reserved0 [31:31] */
#define BCHP_MEMC_GEN_0_ARC_0_VIOLATION_INFO_CMD_reserved0_MASK    0x80000000
#define BCHP_MEMC_GEN_0_ARC_0_VIOLATION_INFO_CMD_reserved0_SHIFT   31

/* MEMC_GEN_0 :: ARC_0_VIOLATION_INFO_CMD :: CLIENTID [30:24] */
#define BCHP_MEMC_GEN_0_ARC_0_VIOLATION_INFO_CMD_CLIENTID_MASK     0x7f000000
#define BCHP_MEMC_GEN_0_ARC_0_VIOLATION_INFO_CMD_CLIENTID_SHIFT    24
#define BCHP_MEMC_GEN_0_ARC_0_VIOLATION_INFO_CMD_CLIENTID_DEFAULT  0

/* MEMC_GEN_0 :: ARC_0_VIOLATION_INFO_CMD :: reserved1 [23:22] */
#define BCHP_MEMC_GEN_0_ARC_0_VIOLATION_INFO_CMD_reserved1_MASK    0x00c00000
#define BCHP_MEMC_GEN_0_ARC_0_VIOLATION_INFO_CMD_reserved1_SHIFT   22

/* MEMC_GEN_0 :: ARC_0_VIOLATION_INFO_CMD :: NMB [21:12] */
#define BCHP_MEMC_GEN_0_ARC_0_VIOLATION_INFO_CMD_NMB_MASK          0x003ff000
#define BCHP_MEMC_GEN_0_ARC_0_VIOLATION_INFO_CMD_NMB_SHIFT         12
#define BCHP_MEMC_GEN_0_ARC_0_VIOLATION_INFO_CMD_NMB_DEFAULT       0

/* MEMC_GEN_0 :: ARC_0_VIOLATION_INFO_CMD :: reserved2 [11:09] */
#define BCHP_MEMC_GEN_0_ARC_0_VIOLATION_INFO_CMD_reserved2_MASK    0x00000e00
#define BCHP_MEMC_GEN_0_ARC_0_VIOLATION_INFO_CMD_reserved2_SHIFT   9

/* MEMC_GEN_0 :: ARC_0_VIOLATION_INFO_CMD :: REQ_TYPE [08:00] */
#define BCHP_MEMC_GEN_0_ARC_0_VIOLATION_INFO_CMD_REQ_TYPE_MASK     0x000001ff
#define BCHP_MEMC_GEN_0_ARC_0_VIOLATION_INFO_CMD_REQ_TYPE_SHIFT    0
#define BCHP_MEMC_GEN_0_ARC_0_VIOLATION_INFO_CMD_REQ_TYPE_DEFAULT  0

/***************************************************************************
 *ARC_0_VIOLATION_INFO_CLEAR - ARCH0 violation info write clear register
 ***************************************************************************/
/* MEMC_GEN_0 :: ARC_0_VIOLATION_INFO_CLEAR :: reserved0 [31:01] */
#define BCHP_MEMC_GEN_0_ARC_0_VIOLATION_INFO_CLEAR_reserved0_MASK  0xfffffffe
#define BCHP_MEMC_GEN_0_ARC_0_VIOLATION_INFO_CLEAR_reserved0_SHIFT 1

/* MEMC_GEN_0 :: ARC_0_VIOLATION_INFO_CLEAR :: WRITE_CLEAR [00:00] */
#define BCHP_MEMC_GEN_0_ARC_0_VIOLATION_INFO_CLEAR_WRITE_CLEAR_MASK 0x00000001
#define BCHP_MEMC_GEN_0_ARC_0_VIOLATION_INFO_CLEAR_WRITE_CLEAR_SHIFT 0
#define BCHP_MEMC_GEN_0_ARC_0_VIOLATION_INFO_CLEAR_WRITE_CLEAR_DEFAULT 0

/***************************************************************************
 *ARC_1_CNTRL - Mode/Control register for Address Range Checker (ARC)-1
 ***************************************************************************/
/* MEMC_GEN_0 :: ARC_1_CNTRL :: reserved0 [31:05] */
#define BCHP_MEMC_GEN_0_ARC_1_CNTRL_reserved0_MASK                 0xffffffe0
#define BCHP_MEMC_GEN_0_ARC_1_CNTRL_reserved0_SHIFT                5

/* MEMC_GEN_0 :: ARC_1_CNTRL :: WRITE_CMD_ABORT [04:04] */
#define BCHP_MEMC_GEN_0_ARC_1_CNTRL_WRITE_CMD_ABORT_MASK           0x00000010
#define BCHP_MEMC_GEN_0_ARC_1_CNTRL_WRITE_CMD_ABORT_SHIFT          4
#define BCHP_MEMC_GEN_0_ARC_1_CNTRL_WRITE_CMD_ABORT_DEFAULT        0
#define BCHP_MEMC_GEN_0_ARC_1_CNTRL_WRITE_CMD_ABORT_DISABLED       0
#define BCHP_MEMC_GEN_0_ARC_1_CNTRL_WRITE_CMD_ABORT_ENABLED        1

/* MEMC_GEN_0 :: ARC_1_CNTRL :: WRITE_CHECK [03:03] */
#define BCHP_MEMC_GEN_0_ARC_1_CNTRL_WRITE_CHECK_MASK               0x00000008
#define BCHP_MEMC_GEN_0_ARC_1_CNTRL_WRITE_CHECK_SHIFT              3
#define BCHP_MEMC_GEN_0_ARC_1_CNTRL_WRITE_CHECK_DEFAULT            0
#define BCHP_MEMC_GEN_0_ARC_1_CNTRL_WRITE_CHECK_DISABLED           0
#define BCHP_MEMC_GEN_0_ARC_1_CNTRL_WRITE_CHECK_ENABLED            1

/* MEMC_GEN_0 :: ARC_1_CNTRL :: READ_CMD_ABORT [02:02] */
#define BCHP_MEMC_GEN_0_ARC_1_CNTRL_READ_CMD_ABORT_MASK            0x00000004
#define BCHP_MEMC_GEN_0_ARC_1_CNTRL_READ_CMD_ABORT_SHIFT           2
#define BCHP_MEMC_GEN_0_ARC_1_CNTRL_READ_CMD_ABORT_DEFAULT         0
#define BCHP_MEMC_GEN_0_ARC_1_CNTRL_READ_CMD_ABORT_DISABLED        0
#define BCHP_MEMC_GEN_0_ARC_1_CNTRL_READ_CMD_ABORT_ENABLED         1

/* MEMC_GEN_0 :: ARC_1_CNTRL :: READ_CHECK [01:01] */
#define BCHP_MEMC_GEN_0_ARC_1_CNTRL_READ_CHECK_MASK                0x00000002
#define BCHP_MEMC_GEN_0_ARC_1_CNTRL_READ_CHECK_SHIFT               1
#define BCHP_MEMC_GEN_0_ARC_1_CNTRL_READ_CHECK_DEFAULT             0
#define BCHP_MEMC_GEN_0_ARC_1_CNTRL_READ_CHECK_DISABLED            0
#define BCHP_MEMC_GEN_0_ARC_1_CNTRL_READ_CHECK_ENABLED             1

/* MEMC_GEN_0 :: ARC_1_CNTRL :: MODE [00:00] */
#define BCHP_MEMC_GEN_0_ARC_1_CNTRL_MODE_MASK                      0x00000001
#define BCHP_MEMC_GEN_0_ARC_1_CNTRL_MODE_SHIFT                     0
#define BCHP_MEMC_GEN_0_ARC_1_CNTRL_MODE_DEFAULT                   0
#define BCHP_MEMC_GEN_0_ARC_1_CNTRL_MODE_NON_EXCLUSIVE             0
#define BCHP_MEMC_GEN_0_ARC_1_CNTRL_MODE_EXCLUSIVE                 1

/***************************************************************************
 *ARC_1_ADRS_RANGE_LOW - Lower Address of the memory range for Address Range Checker (ARC)-1.
 ***************************************************************************/
/* MEMC_GEN_0 :: ARC_1_ADRS_RANGE_LOW :: reserved0 [31:29] */
#define BCHP_MEMC_GEN_0_ARC_1_ADRS_RANGE_LOW_reserved0_MASK        0xe0000000
#define BCHP_MEMC_GEN_0_ARC_1_ADRS_RANGE_LOW_reserved0_SHIFT       29

/* MEMC_GEN_0 :: ARC_1_ADRS_RANGE_LOW :: ADDRESS [28:00] */
#define BCHP_MEMC_GEN_0_ARC_1_ADRS_RANGE_LOW_ADDRESS_MASK          0x1fffffff
#define BCHP_MEMC_GEN_0_ARC_1_ADRS_RANGE_LOW_ADDRESS_SHIFT         0
#define BCHP_MEMC_GEN_0_ARC_1_ADRS_RANGE_LOW_ADDRESS_DEFAULT       0

/***************************************************************************
 *ARC_1_ADRS_RANGE_HIGH - Higher Address of the memory range for Address Range Checker (ARC)-1.
 ***************************************************************************/
/* MEMC_GEN_0 :: ARC_1_ADRS_RANGE_HIGH :: reserved0 [31:29] */
#define BCHP_MEMC_GEN_0_ARC_1_ADRS_RANGE_HIGH_reserved0_MASK       0xe0000000
#define BCHP_MEMC_GEN_0_ARC_1_ADRS_RANGE_HIGH_reserved0_SHIFT      29

/* MEMC_GEN_0 :: ARC_1_ADRS_RANGE_HIGH :: ADDRESS [28:00] */
#define BCHP_MEMC_GEN_0_ARC_1_ADRS_RANGE_HIGH_ADDRESS_MASK         0x1fffffff
#define BCHP_MEMC_GEN_0_ARC_1_ADRS_RANGE_HIGH_ADDRESS_SHIFT        0
#define BCHP_MEMC_GEN_0_ARC_1_ADRS_RANGE_HIGH_ADDRESS_DEFAULT      0

/***************************************************************************
 *ARC_1_READ_RIGHTS_0 - Read access right of SCB clients 0 to 31 on Address Range Checker (ARC)-1
 ***************************************************************************/
/* MEMC_GEN_0 :: ARC_1_READ_RIGHTS_0 :: ACCESS_RIGHT [31:00] */
#define BCHP_MEMC_GEN_0_ARC_1_READ_RIGHTS_0_ACCESS_RIGHT_MASK      0xffffffff
#define BCHP_MEMC_GEN_0_ARC_1_READ_RIGHTS_0_ACCESS_RIGHT_SHIFT     0
#define BCHP_MEMC_GEN_0_ARC_1_READ_RIGHTS_0_ACCESS_RIGHT_DEFAULT   0

/***************************************************************************
 *ARC_1_READ_RIGHTS_1 - Read access right of SCB clients 32 to 63 on Address Range Checker(ARC)-1
 ***************************************************************************/
/* MEMC_GEN_0 :: ARC_1_READ_RIGHTS_1 :: ACCESS_RIGHT [31:00] */
#define BCHP_MEMC_GEN_0_ARC_1_READ_RIGHTS_1_ACCESS_RIGHT_MASK      0xffffffff
#define BCHP_MEMC_GEN_0_ARC_1_READ_RIGHTS_1_ACCESS_RIGHT_SHIFT     0
#define BCHP_MEMC_GEN_0_ARC_1_READ_RIGHTS_1_ACCESS_RIGHT_DEFAULT   0

/***************************************************************************
 *ARC_1_READ_RIGHTS_2 - Read access right of SCB clients 64 to 95 on Address Range Checker (ARC)-1
 ***************************************************************************/
/* MEMC_GEN_0 :: ARC_1_READ_RIGHTS_2 :: ACCESS_RIGHT [31:00] */
#define BCHP_MEMC_GEN_0_ARC_1_READ_RIGHTS_2_ACCESS_RIGHT_MASK      0xffffffff
#define BCHP_MEMC_GEN_0_ARC_1_READ_RIGHTS_2_ACCESS_RIGHT_SHIFT     0
#define BCHP_MEMC_GEN_0_ARC_1_READ_RIGHTS_2_ACCESS_RIGHT_DEFAULT   0

/***************************************************************************
 *ARC_1_READ_RIGHTS_3 - Read access right of SCB clients 96 to 127 on Address Range Checker(ARC)-1
 ***************************************************************************/
/* MEMC_GEN_0 :: ARC_1_READ_RIGHTS_3 :: ACCESS_RIGHT [31:00] */
#define BCHP_MEMC_GEN_0_ARC_1_READ_RIGHTS_3_ACCESS_RIGHT_MASK      0xffffffff
#define BCHP_MEMC_GEN_0_ARC_1_READ_RIGHTS_3_ACCESS_RIGHT_SHIFT     0
#define BCHP_MEMC_GEN_0_ARC_1_READ_RIGHTS_3_ACCESS_RIGHT_DEFAULT   0

/***************************************************************************
 *ARC_1_WRITE_RIGHTS_0 - Write access right of SCB clients 0 to 31 on Address Range Checker(ARC)-1
 ***************************************************************************/
/* MEMC_GEN_0 :: ARC_1_WRITE_RIGHTS_0 :: ACCESS_RIGHT [31:00] */
#define BCHP_MEMC_GEN_0_ARC_1_WRITE_RIGHTS_0_ACCESS_RIGHT_MASK     0xffffffff
#define BCHP_MEMC_GEN_0_ARC_1_WRITE_RIGHTS_0_ACCESS_RIGHT_SHIFT    0
#define BCHP_MEMC_GEN_0_ARC_1_WRITE_RIGHTS_0_ACCESS_RIGHT_DEFAULT  0

/***************************************************************************
 *ARC_1_WRITE_RIGHTS_1 - Write access right of SCB clients 32 to 63 on Address Range Checker(ARC)-1
 ***************************************************************************/
/* MEMC_GEN_0 :: ARC_1_WRITE_RIGHTS_1 :: ACCESS_RIGHT [31:00] */
#define BCHP_MEMC_GEN_0_ARC_1_WRITE_RIGHTS_1_ACCESS_RIGHT_MASK     0xffffffff
#define BCHP_MEMC_GEN_0_ARC_1_WRITE_RIGHTS_1_ACCESS_RIGHT_SHIFT    0
#define BCHP_MEMC_GEN_0_ARC_1_WRITE_RIGHTS_1_ACCESS_RIGHT_DEFAULT  0

/***************************************************************************
 *ARC_1_WRITE_RIGHTS_2 - Write access right of SCB clients 0 to 31 on Address Range Checker(ARC)-1
 ***************************************************************************/
/* MEMC_GEN_0 :: ARC_1_WRITE_RIGHTS_2 :: ACCESS_RIGHT [31:00] */
#define BCHP_MEMC_GEN_0_ARC_1_WRITE_RIGHTS_2_ACCESS_RIGHT_MASK     0xffffffff
#define BCHP_MEMC_GEN_0_ARC_1_WRITE_RIGHTS_2_ACCESS_RIGHT_SHIFT    0
#define BCHP_MEMC_GEN_0_ARC_1_WRITE_RIGHTS_2_ACCESS_RIGHT_DEFAULT  0

/***************************************************************************
 *ARC_1_WRITE_RIGHTS_3 - Write access right of SCB clients 32 to 63 on Address Range Checker(ARC)-1
 ***************************************************************************/
/* MEMC_GEN_0 :: ARC_1_WRITE_RIGHTS_3 :: ACCESS_RIGHT [31:00] */
#define BCHP_MEMC_GEN_0_ARC_1_WRITE_RIGHTS_3_ACCESS_RIGHT_MASK     0xffffffff
#define BCHP_MEMC_GEN_0_ARC_1_WRITE_RIGHTS_3_ACCESS_RIGHT_SHIFT    0
#define BCHP_MEMC_GEN_0_ARC_1_WRITE_RIGHTS_3_ACCESS_RIGHT_DEFAULT  0

/***************************************************************************
 *ARC_1_VIOLATION_INFO_START_ADDR - Violating Command Start Address for Address Range Checker (ARC)-1 .
 ***************************************************************************/
/* MEMC_GEN_0 :: ARC_1_VIOLATION_INFO_START_ADDR :: reserved0 [31:29] */
#define BCHP_MEMC_GEN_0_ARC_1_VIOLATION_INFO_START_ADDR_reserved0_MASK 0xe0000000
#define BCHP_MEMC_GEN_0_ARC_1_VIOLATION_INFO_START_ADDR_reserved0_SHIFT 29

/* MEMC_GEN_0 :: ARC_1_VIOLATION_INFO_START_ADDR :: ADDRESS [28:00] */
#define BCHP_MEMC_GEN_0_ARC_1_VIOLATION_INFO_START_ADDR_ADDRESS_MASK 0x1fffffff
#define BCHP_MEMC_GEN_0_ARC_1_VIOLATION_INFO_START_ADDR_ADDRESS_SHIFT 0
#define BCHP_MEMC_GEN_0_ARC_1_VIOLATION_INFO_START_ADDR_ADDRESS_DEFAULT 0

/***************************************************************************
 *ARC_1_VIOLATION_INFO_END_ADDR - Violating Command End Address for Address Range Checker (ARC)-1 .
 ***************************************************************************/
/* MEMC_GEN_0 :: ARC_1_VIOLATION_INFO_END_ADDR :: reserved0 [31:29] */
#define BCHP_MEMC_GEN_0_ARC_1_VIOLATION_INFO_END_ADDR_reserved0_MASK 0xe0000000
#define BCHP_MEMC_GEN_0_ARC_1_VIOLATION_INFO_END_ADDR_reserved0_SHIFT 29

/* MEMC_GEN_0 :: ARC_1_VIOLATION_INFO_END_ADDR :: ADDRESS [28:00] */
#define BCHP_MEMC_GEN_0_ARC_1_VIOLATION_INFO_END_ADDR_ADDRESS_MASK 0x1fffffff
#define BCHP_MEMC_GEN_0_ARC_1_VIOLATION_INFO_END_ADDR_ADDRESS_SHIFT 0
#define BCHP_MEMC_GEN_0_ARC_1_VIOLATION_INFO_END_ADDR_ADDRESS_DEFAULT 0

/***************************************************************************
 *ARC_1_VIOLATION_INFO_CMD - Violating SCB client-ID & Command Type for Address Range Checker (ARC)-1 .
 ***************************************************************************/
/* MEMC_GEN_0 :: ARC_1_VIOLATION_INFO_CMD :: reserved0 [31:31] */
#define BCHP_MEMC_GEN_0_ARC_1_VIOLATION_INFO_CMD_reserved0_MASK    0x80000000
#define BCHP_MEMC_GEN_0_ARC_1_VIOLATION_INFO_CMD_reserved0_SHIFT   31

/* MEMC_GEN_0 :: ARC_1_VIOLATION_INFO_CMD :: CLIENTID [30:24] */
#define BCHP_MEMC_GEN_0_ARC_1_VIOLATION_INFO_CMD_CLIENTID_MASK     0x7f000000
#define BCHP_MEMC_GEN_0_ARC_1_VIOLATION_INFO_CMD_CLIENTID_SHIFT    24
#define BCHP_MEMC_GEN_0_ARC_1_VIOLATION_INFO_CMD_CLIENTID_DEFAULT  0

/* MEMC_GEN_0 :: ARC_1_VIOLATION_INFO_CMD :: reserved1 [23:22] */
#define BCHP_MEMC_GEN_0_ARC_1_VIOLATION_INFO_CMD_reserved1_MASK    0x00c00000
#define BCHP_MEMC_GEN_0_ARC_1_VIOLATION_INFO_CMD_reserved1_SHIFT   22

/* MEMC_GEN_0 :: ARC_1_VIOLATION_INFO_CMD :: NMB [21:12] */
#define BCHP_MEMC_GEN_0_ARC_1_VIOLATION_INFO_CMD_NMB_MASK          0x003ff000
#define BCHP_MEMC_GEN_0_ARC_1_VIOLATION_INFO_CMD_NMB_SHIFT         12
#define BCHP_MEMC_GEN_0_ARC_1_VIOLATION_INFO_CMD_NMB_DEFAULT       0

/* MEMC_GEN_0 :: ARC_1_VIOLATION_INFO_CMD :: reserved2 [11:09] */
#define BCHP_MEMC_GEN_0_ARC_1_VIOLATION_INFO_CMD_reserved2_MASK    0x00000e00
#define BCHP_MEMC_GEN_0_ARC_1_VIOLATION_INFO_CMD_reserved2_SHIFT   9

/* MEMC_GEN_0 :: ARC_1_VIOLATION_INFO_CMD :: REQ_TYPE [08:00] */
#define BCHP_MEMC_GEN_0_ARC_1_VIOLATION_INFO_CMD_REQ_TYPE_MASK     0x000001ff
#define BCHP_MEMC_GEN_0_ARC_1_VIOLATION_INFO_CMD_REQ_TYPE_SHIFT    0
#define BCHP_MEMC_GEN_0_ARC_1_VIOLATION_INFO_CMD_REQ_TYPE_DEFAULT  0

/***************************************************************************
 *ARC_1_VIOLATION_INFO_CLEAR - ARCH1 violation info write clear register
 ***************************************************************************/
/* MEMC_GEN_0 :: ARC_1_VIOLATION_INFO_CLEAR :: reserved0 [31:01] */
#define BCHP_MEMC_GEN_0_ARC_1_VIOLATION_INFO_CLEAR_reserved0_MASK  0xfffffffe
#define BCHP_MEMC_GEN_0_ARC_1_VIOLATION_INFO_CLEAR_reserved0_SHIFT 1

/* MEMC_GEN_0 :: ARC_1_VIOLATION_INFO_CLEAR :: WRITE_CLEAR [00:00] */
#define BCHP_MEMC_GEN_0_ARC_1_VIOLATION_INFO_CLEAR_WRITE_CLEAR_MASK 0x00000001
#define BCHP_MEMC_GEN_0_ARC_1_VIOLATION_INFO_CLEAR_WRITE_CLEAR_SHIFT 0
#define BCHP_MEMC_GEN_0_ARC_1_VIOLATION_INFO_CLEAR_WRITE_CLEAR_DEFAULT 0

/***************************************************************************
 *ARC_2_CNTRL - Mode/Control register for Address Range Checker (ARC)-2
 ***************************************************************************/
/* MEMC_GEN_0 :: ARC_2_CNTRL :: reserved0 [31:05] */
#define BCHP_MEMC_GEN_0_ARC_2_CNTRL_reserved0_MASK                 0xffffffe0
#define BCHP_MEMC_GEN_0_ARC_2_CNTRL_reserved0_SHIFT                5

/* MEMC_GEN_0 :: ARC_2_CNTRL :: WRITE_CMD_ABORT [04:04] */
#define BCHP_MEMC_GEN_0_ARC_2_CNTRL_WRITE_CMD_ABORT_MASK           0x00000010
#define BCHP_MEMC_GEN_0_ARC_2_CNTRL_WRITE_CMD_ABORT_SHIFT          4
#define BCHP_MEMC_GEN_0_ARC_2_CNTRL_WRITE_CMD_ABORT_DEFAULT        0
#define BCHP_MEMC_GEN_0_ARC_2_CNTRL_WRITE_CMD_ABORT_DISABLED       0
#define BCHP_MEMC_GEN_0_ARC_2_CNTRL_WRITE_CMD_ABORT_ENABLED        1

/* MEMC_GEN_0 :: ARC_2_CNTRL :: WRITE_CHECK [03:03] */
#define BCHP_MEMC_GEN_0_ARC_2_CNTRL_WRITE_CHECK_MASK               0x00000008
#define BCHP_MEMC_GEN_0_ARC_2_CNTRL_WRITE_CHECK_SHIFT              3
#define BCHP_MEMC_GEN_0_ARC_2_CNTRL_WRITE_CHECK_DEFAULT            0
#define BCHP_MEMC_GEN_0_ARC_2_CNTRL_WRITE_CHECK_DISABLED           0
#define BCHP_MEMC_GEN_0_ARC_2_CNTRL_WRITE_CHECK_ENABLED            1

/* MEMC_GEN_0 :: ARC_2_CNTRL :: READ_CMD_ABORT [02:02] */
#define BCHP_MEMC_GEN_0_ARC_2_CNTRL_READ_CMD_ABORT_MASK            0x00000004
#define BCHP_MEMC_GEN_0_ARC_2_CNTRL_READ_CMD_ABORT_SHIFT           2
#define BCHP_MEMC_GEN_0_ARC_2_CNTRL_READ_CMD_ABORT_DEFAULT         0
#define BCHP_MEMC_GEN_0_ARC_2_CNTRL_READ_CMD_ABORT_DISABLED        0
#define BCHP_MEMC_GEN_0_ARC_2_CNTRL_READ_CMD_ABORT_ENABLED         1

/* MEMC_GEN_0 :: ARC_2_CNTRL :: READ_CHECK [01:01] */
#define BCHP_MEMC_GEN_0_ARC_2_CNTRL_READ_CHECK_MASK                0x00000002
#define BCHP_MEMC_GEN_0_ARC_2_CNTRL_READ_CHECK_SHIFT               1
#define BCHP_MEMC_GEN_0_ARC_2_CNTRL_READ_CHECK_DEFAULT             0
#define BCHP_MEMC_GEN_0_ARC_2_CNTRL_READ_CHECK_DISABLED            0
#define BCHP_MEMC_GEN_0_ARC_2_CNTRL_READ_CHECK_ENABLED             1

/* MEMC_GEN_0 :: ARC_2_CNTRL :: MODE [00:00] */
#define BCHP_MEMC_GEN_0_ARC_2_CNTRL_MODE_MASK                      0x00000001
#define BCHP_MEMC_GEN_0_ARC_2_CNTRL_MODE_SHIFT                     0
#define BCHP_MEMC_GEN_0_ARC_2_CNTRL_MODE_DEFAULT                   0
#define BCHP_MEMC_GEN_0_ARC_2_CNTRL_MODE_NON_EXCLUSIVE             0
#define BCHP_MEMC_GEN_0_ARC_2_CNTRL_MODE_EXCLUSIVE                 1

/***************************************************************************
 *ARC_2_ADRS_RANGE_LOW - Lower Address of the memory range for Address Range Checker (ARC)-2.
 ***************************************************************************/
/* MEMC_GEN_0 :: ARC_2_ADRS_RANGE_LOW :: reserved0 [31:29] */
#define BCHP_MEMC_GEN_0_ARC_2_ADRS_RANGE_LOW_reserved0_MASK        0xe0000000
#define BCHP_MEMC_GEN_0_ARC_2_ADRS_RANGE_LOW_reserved0_SHIFT       29

/* MEMC_GEN_0 :: ARC_2_ADRS_RANGE_LOW :: ADDRESS [28:00] */
#define BCHP_MEMC_GEN_0_ARC_2_ADRS_RANGE_LOW_ADDRESS_MASK          0x1fffffff
#define BCHP_MEMC_GEN_0_ARC_2_ADRS_RANGE_LOW_ADDRESS_SHIFT         0
#define BCHP_MEMC_GEN_0_ARC_2_ADRS_RANGE_LOW_ADDRESS_DEFAULT       0

/***************************************************************************
 *ARC_2_ADRS_RANGE_HIGH - Higher Address of the memory range for Address Range Checker (ARC)-2.
 ***************************************************************************/
/* MEMC_GEN_0 :: ARC_2_ADRS_RANGE_HIGH :: reserved0 [31:29] */
#define BCHP_MEMC_GEN_0_ARC_2_ADRS_RANGE_HIGH_reserved0_MASK       0xe0000000
#define BCHP_MEMC_GEN_0_ARC_2_ADRS_RANGE_HIGH_reserved0_SHIFT      29

/* MEMC_GEN_0 :: ARC_2_ADRS_RANGE_HIGH :: ADDRESS [28:00] */
#define BCHP_MEMC_GEN_0_ARC_2_ADRS_RANGE_HIGH_ADDRESS_MASK         0x1fffffff
#define BCHP_MEMC_GEN_0_ARC_2_ADRS_RANGE_HIGH_ADDRESS_SHIFT        0
#define BCHP_MEMC_GEN_0_ARC_2_ADRS_RANGE_HIGH_ADDRESS_DEFAULT      0

/***************************************************************************
 *ARC_2_READ_RIGHTS_0 - Read access right of SCB clients 0 to 31 on Address Range Checker (ARC)-2
 ***************************************************************************/
/* MEMC_GEN_0 :: ARC_2_READ_RIGHTS_0 :: ACCESS_RIGHT [31:00] */
#define BCHP_MEMC_GEN_0_ARC_2_READ_RIGHTS_0_ACCESS_RIGHT_MASK      0xffffffff
#define BCHP_MEMC_GEN_0_ARC_2_READ_RIGHTS_0_ACCESS_RIGHT_SHIFT     0
#define BCHP_MEMC_GEN_0_ARC_2_READ_RIGHTS_0_ACCESS_RIGHT_DEFAULT   0

/***************************************************************************
 *ARC_2_READ_RIGHTS_1 - Read access right of SCB clients 32 to 63 on Address Range Checker(ARC)-2
 ***************************************************************************/
/* MEMC_GEN_0 :: ARC_2_READ_RIGHTS_1 :: ACCESS_RIGHT [31:00] */
#define BCHP_MEMC_GEN_0_ARC_2_READ_RIGHTS_1_ACCESS_RIGHT_MASK      0xffffffff
#define BCHP_MEMC_GEN_0_ARC_2_READ_RIGHTS_1_ACCESS_RIGHT_SHIFT     0
#define BCHP_MEMC_GEN_0_ARC_2_READ_RIGHTS_1_ACCESS_RIGHT_DEFAULT   0

/***************************************************************************
 *ARC_2_READ_RIGHTS_2 - Read access right of SCB clients 64 to 95 on Address Range Checker (ARC)-2
 ***************************************************************************/
/* MEMC_GEN_0 :: ARC_2_READ_RIGHTS_2 :: ACCESS_RIGHT [31:00] */
#define BCHP_MEMC_GEN_0_ARC_2_READ_RIGHTS_2_ACCESS_RIGHT_MASK      0xffffffff
#define BCHP_MEMC_GEN_0_ARC_2_READ_RIGHTS_2_ACCESS_RIGHT_SHIFT     0
#define BCHP_MEMC_GEN_0_ARC_2_READ_RIGHTS_2_ACCESS_RIGHT_DEFAULT   0

/***************************************************************************
 *ARC_2_READ_RIGHTS_3 - Read access right of SCB clients 96 to 127 on Address Range Checker(ARC)-2
 ***************************************************************************/
/* MEMC_GEN_0 :: ARC_2_READ_RIGHTS_3 :: ACCESS_RIGHT [31:00] */
#define BCHP_MEMC_GEN_0_ARC_2_READ_RIGHTS_3_ACCESS_RIGHT_MASK      0xffffffff
#define BCHP_MEMC_GEN_0_ARC_2_READ_RIGHTS_3_ACCESS_RIGHT_SHIFT     0
#define BCHP_MEMC_GEN_0_ARC_2_READ_RIGHTS_3_ACCESS_RIGHT_DEFAULT   0

/***************************************************************************
 *ARC_2_WRITE_RIGHTS_0 - Write access right of SCB clients 0 to 31 on Address Range Checker(ARC)-2
 ***************************************************************************/
/* MEMC_GEN_0 :: ARC_2_WRITE_RIGHTS_0 :: ACCESS_RIGHT [31:00] */
#define BCHP_MEMC_GEN_0_ARC_2_WRITE_RIGHTS_0_ACCESS_RIGHT_MASK     0xffffffff
#define BCHP_MEMC_GEN_0_ARC_2_WRITE_RIGHTS_0_ACCESS_RIGHT_SHIFT    0
#define BCHP_MEMC_GEN_0_ARC_2_WRITE_RIGHTS_0_ACCESS_RIGHT_DEFAULT  0

/***************************************************************************
 *ARC_2_WRITE_RIGHTS_1 - Write access right of SCB clients 32 to 63 on Address Range Checker(ARC)-2
 ***************************************************************************/
/* MEMC_GEN_0 :: ARC_2_WRITE_RIGHTS_1 :: ACCESS_RIGHT [31:00] */
#define BCHP_MEMC_GEN_0_ARC_2_WRITE_RIGHTS_1_ACCESS_RIGHT_MASK     0xffffffff
#define BCHP_MEMC_GEN_0_ARC_2_WRITE_RIGHTS_1_ACCESS_RIGHT_SHIFT    0
#define BCHP_MEMC_GEN_0_ARC_2_WRITE_RIGHTS_1_ACCESS_RIGHT_DEFAULT  0

/***************************************************************************
 *ARC_2_WRITE_RIGHTS_2 - Write access right of SCB clients 0 to 31 on Address Range Checker(ARC)-2
 ***************************************************************************/
/* MEMC_GEN_0 :: ARC_2_WRITE_RIGHTS_2 :: ACCESS_RIGHT [31:00] */
#define BCHP_MEMC_GEN_0_ARC_2_WRITE_RIGHTS_2_ACCESS_RIGHT_MASK     0xffffffff
#define BCHP_MEMC_GEN_0_ARC_2_WRITE_RIGHTS_2_ACCESS_RIGHT_SHIFT    0
#define BCHP_MEMC_GEN_0_ARC_2_WRITE_RIGHTS_2_ACCESS_RIGHT_DEFAULT  0

/***************************************************************************
 *ARC_2_WRITE_RIGHTS_3 - Write access right of SCB clients 32 to 63 on Address Range Checker(ARC)-2
 ***************************************************************************/
/* MEMC_GEN_0 :: ARC_2_WRITE_RIGHTS_3 :: ACCESS_RIGHT [31:00] */
#define BCHP_MEMC_GEN_0_ARC_2_WRITE_RIGHTS_3_ACCESS_RIGHT_MASK     0xffffffff
#define BCHP_MEMC_GEN_0_ARC_2_WRITE_RIGHTS_3_ACCESS_RIGHT_SHIFT    0
#define BCHP_MEMC_GEN_0_ARC_2_WRITE_RIGHTS_3_ACCESS_RIGHT_DEFAULT  0

/***************************************************************************
 *ARC_2_VIOLATION_INFO_START_ADDR - Violating Command Start Address for Address Range Checker (ARC)-2 .
 ***************************************************************************/
/* MEMC_GEN_0 :: ARC_2_VIOLATION_INFO_START_ADDR :: reserved0 [31:29] */
#define BCHP_MEMC_GEN_0_ARC_2_VIOLATION_INFO_START_ADDR_reserved0_MASK 0xe0000000
#define BCHP_MEMC_GEN_0_ARC_2_VIOLATION_INFO_START_ADDR_reserved0_SHIFT 29

/* MEMC_GEN_0 :: ARC_2_VIOLATION_INFO_START_ADDR :: ADDRESS [28:00] */
#define BCHP_MEMC_GEN_0_ARC_2_VIOLATION_INFO_START_ADDR_ADDRESS_MASK 0x1fffffff
#define BCHP_MEMC_GEN_0_ARC_2_VIOLATION_INFO_START_ADDR_ADDRESS_SHIFT 0
#define BCHP_MEMC_GEN_0_ARC_2_VIOLATION_INFO_START_ADDR_ADDRESS_DEFAULT 0

/***************************************************************************
 *ARC_2_VIOLATION_INFO_END_ADDR - Violating Command End Address for Address Range Checker (ARC)-2 .
 ***************************************************************************/
/* MEMC_GEN_0 :: ARC_2_VIOLATION_INFO_END_ADDR :: reserved0 [31:29] */
#define BCHP_MEMC_GEN_0_ARC_2_VIOLATION_INFO_END_ADDR_reserved0_MASK 0xe0000000
#define BCHP_MEMC_GEN_0_ARC_2_VIOLATION_INFO_END_ADDR_reserved0_SHIFT 29

/* MEMC_GEN_0 :: ARC_2_VIOLATION_INFO_END_ADDR :: ADDRESS [28:00] */
#define BCHP_MEMC_GEN_0_ARC_2_VIOLATION_INFO_END_ADDR_ADDRESS_MASK 0x1fffffff
#define BCHP_MEMC_GEN_0_ARC_2_VIOLATION_INFO_END_ADDR_ADDRESS_SHIFT 0
#define BCHP_MEMC_GEN_0_ARC_2_VIOLATION_INFO_END_ADDR_ADDRESS_DEFAULT 0

/***************************************************************************
 *ARC_2_VIOLATION_INFO_CMD - Violating SCB client-ID & Command Type for Address Range Checker (ARC)-2 .
 ***************************************************************************/
/* MEMC_GEN_0 :: ARC_2_VIOLATION_INFO_CMD :: reserved0 [31:31] */
#define BCHP_MEMC_GEN_0_ARC_2_VIOLATION_INFO_CMD_reserved0_MASK    0x80000000
#define BCHP_MEMC_GEN_0_ARC_2_VIOLATION_INFO_CMD_reserved0_SHIFT   31

/* MEMC_GEN_0 :: ARC_2_VIOLATION_INFO_CMD :: CLIENTID [30:24] */
#define BCHP_MEMC_GEN_0_ARC_2_VIOLATION_INFO_CMD_CLIENTID_MASK     0x7f000000
#define BCHP_MEMC_GEN_0_ARC_2_VIOLATION_INFO_CMD_CLIENTID_SHIFT    24
#define BCHP_MEMC_GEN_0_ARC_2_VIOLATION_INFO_CMD_CLIENTID_DEFAULT  0

/* MEMC_GEN_0 :: ARC_2_VIOLATION_INFO_CMD :: reserved1 [23:22] */
#define BCHP_MEMC_GEN_0_ARC_2_VIOLATION_INFO_CMD_reserved1_MASK    0x00c00000
#define BCHP_MEMC_GEN_0_ARC_2_VIOLATION_INFO_CMD_reserved1_SHIFT   22

/* MEMC_GEN_0 :: ARC_2_VIOLATION_INFO_CMD :: NMB [21:12] */
#define BCHP_MEMC_GEN_0_ARC_2_VIOLATION_INFO_CMD_NMB_MASK          0x003ff000
#define BCHP_MEMC_GEN_0_ARC_2_VIOLATION_INFO_CMD_NMB_SHIFT         12
#define BCHP_MEMC_GEN_0_ARC_2_VIOLATION_INFO_CMD_NMB_DEFAULT       0

/* MEMC_GEN_0 :: ARC_2_VIOLATION_INFO_CMD :: reserved2 [11:09] */
#define BCHP_MEMC_GEN_0_ARC_2_VIOLATION_INFO_CMD_reserved2_MASK    0x00000e00
#define BCHP_MEMC_GEN_0_ARC_2_VIOLATION_INFO_CMD_reserved2_SHIFT   9

/* MEMC_GEN_0 :: ARC_2_VIOLATION_INFO_CMD :: REQ_TYPE [08:00] */
#define BCHP_MEMC_GEN_0_ARC_2_VIOLATION_INFO_CMD_REQ_TYPE_MASK     0x000001ff
#define BCHP_MEMC_GEN_0_ARC_2_VIOLATION_INFO_CMD_REQ_TYPE_SHIFT    0
#define BCHP_MEMC_GEN_0_ARC_2_VIOLATION_INFO_CMD_REQ_TYPE_DEFAULT  0

/***************************************************************************
 *ARC_2_VIOLATION_INFO_CLEAR - ARCH2 violation info write clear register
 ***************************************************************************/
/* MEMC_GEN_0 :: ARC_2_VIOLATION_INFO_CLEAR :: reserved0 [31:01] */
#define BCHP_MEMC_GEN_0_ARC_2_VIOLATION_INFO_CLEAR_reserved0_MASK  0xfffffffe
#define BCHP_MEMC_GEN_0_ARC_2_VIOLATION_INFO_CLEAR_reserved0_SHIFT 1

/* MEMC_GEN_0 :: ARC_2_VIOLATION_INFO_CLEAR :: WRITE_CLEAR [00:00] */
#define BCHP_MEMC_GEN_0_ARC_2_VIOLATION_INFO_CLEAR_WRITE_CLEAR_MASK 0x00000001
#define BCHP_MEMC_GEN_0_ARC_2_VIOLATION_INFO_CLEAR_WRITE_CLEAR_SHIFT 0
#define BCHP_MEMC_GEN_0_ARC_2_VIOLATION_INFO_CLEAR_WRITE_CLEAR_DEFAULT 0

/***************************************************************************
 *ARC_3_CNTRL - Mode/Control register for Address Range Checker (ARC)-3
 ***************************************************************************/
/* MEMC_GEN_0 :: ARC_3_CNTRL :: reserved0 [31:05] */
#define BCHP_MEMC_GEN_0_ARC_3_CNTRL_reserved0_MASK                 0xffffffe0
#define BCHP_MEMC_GEN_0_ARC_3_CNTRL_reserved0_SHIFT                5

/* MEMC_GEN_0 :: ARC_3_CNTRL :: WRITE_CMD_ABORT [04:04] */
#define BCHP_MEMC_GEN_0_ARC_3_CNTRL_WRITE_CMD_ABORT_MASK           0x00000010
#define BCHP_MEMC_GEN_0_ARC_3_CNTRL_WRITE_CMD_ABORT_SHIFT          4
#define BCHP_MEMC_GEN_0_ARC_3_CNTRL_WRITE_CMD_ABORT_DEFAULT        0
#define BCHP_MEMC_GEN_0_ARC_3_CNTRL_WRITE_CMD_ABORT_DISABLED       0
#define BCHP_MEMC_GEN_0_ARC_3_CNTRL_WRITE_CMD_ABORT_ENABLED        1

/* MEMC_GEN_0 :: ARC_3_CNTRL :: WRITE_CHECK [03:03] */
#define BCHP_MEMC_GEN_0_ARC_3_CNTRL_WRITE_CHECK_MASK               0x00000008
#define BCHP_MEMC_GEN_0_ARC_3_CNTRL_WRITE_CHECK_SHIFT              3
#define BCHP_MEMC_GEN_0_ARC_3_CNTRL_WRITE_CHECK_DEFAULT            0
#define BCHP_MEMC_GEN_0_ARC_3_CNTRL_WRITE_CHECK_DISABLED           0
#define BCHP_MEMC_GEN_0_ARC_3_CNTRL_WRITE_CHECK_ENABLED            1

/* MEMC_GEN_0 :: ARC_3_CNTRL :: READ_CMD_ABORT [02:02] */
#define BCHP_MEMC_GEN_0_ARC_3_CNTRL_READ_CMD_ABORT_MASK            0x00000004
#define BCHP_MEMC_GEN_0_ARC_3_CNTRL_READ_CMD_ABORT_SHIFT           2
#define BCHP_MEMC_GEN_0_ARC_3_CNTRL_READ_CMD_ABORT_DEFAULT         0
#define BCHP_MEMC_GEN_0_ARC_3_CNTRL_READ_CMD_ABORT_DISABLED        0
#define BCHP_MEMC_GEN_0_ARC_3_CNTRL_READ_CMD_ABORT_ENABLED         1

/* MEMC_GEN_0 :: ARC_3_CNTRL :: READ_CHECK [01:01] */
#define BCHP_MEMC_GEN_0_ARC_3_CNTRL_READ_CHECK_MASK                0x00000002
#define BCHP_MEMC_GEN_0_ARC_3_CNTRL_READ_CHECK_SHIFT               1
#define BCHP_MEMC_GEN_0_ARC_3_CNTRL_READ_CHECK_DEFAULT             0
#define BCHP_MEMC_GEN_0_ARC_3_CNTRL_READ_CHECK_DISABLED            0
#define BCHP_MEMC_GEN_0_ARC_3_CNTRL_READ_CHECK_ENABLED             1

/* MEMC_GEN_0 :: ARC_3_CNTRL :: MODE [00:00] */
#define BCHP_MEMC_GEN_0_ARC_3_CNTRL_MODE_MASK                      0x00000001
#define BCHP_MEMC_GEN_0_ARC_3_CNTRL_MODE_SHIFT                     0
#define BCHP_MEMC_GEN_0_ARC_3_CNTRL_MODE_DEFAULT                   0
#define BCHP_MEMC_GEN_0_ARC_3_CNTRL_MODE_NON_EXCLUSIVE             0
#define BCHP_MEMC_GEN_0_ARC_3_CNTRL_MODE_EXCLUSIVE                 1

/***************************************************************************
 *ARC_3_ADRS_RANGE_LOW - Lower Address of the memory range for Address Range Checker (ARC)-3.
 ***************************************************************************/
/* MEMC_GEN_0 :: ARC_3_ADRS_RANGE_LOW :: reserved0 [31:29] */
#define BCHP_MEMC_GEN_0_ARC_3_ADRS_RANGE_LOW_reserved0_MASK        0xe0000000
#define BCHP_MEMC_GEN_0_ARC_3_ADRS_RANGE_LOW_reserved0_SHIFT       29

/* MEMC_GEN_0 :: ARC_3_ADRS_RANGE_LOW :: ADDRESS [28:00] */
#define BCHP_MEMC_GEN_0_ARC_3_ADRS_RANGE_LOW_ADDRESS_MASK          0x1fffffff
#define BCHP_MEMC_GEN_0_ARC_3_ADRS_RANGE_LOW_ADDRESS_SHIFT         0
#define BCHP_MEMC_GEN_0_ARC_3_ADRS_RANGE_LOW_ADDRESS_DEFAULT       0

/***************************************************************************
 *ARC_3_ADRS_RANGE_HIGH - Higher Address of the memory range for Address Range Checker (ARC)-3.
 ***************************************************************************/
/* MEMC_GEN_0 :: ARC_3_ADRS_RANGE_HIGH :: reserved0 [31:29] */
#define BCHP_MEMC_GEN_0_ARC_3_ADRS_RANGE_HIGH_reserved0_MASK       0xe0000000
#define BCHP_MEMC_GEN_0_ARC_3_ADRS_RANGE_HIGH_reserved0_SHIFT      29

/* MEMC_GEN_0 :: ARC_3_ADRS_RANGE_HIGH :: ADDRESS [28:00] */
#define BCHP_MEMC_GEN_0_ARC_3_ADRS_RANGE_HIGH_ADDRESS_MASK         0x1fffffff
#define BCHP_MEMC_GEN_0_ARC_3_ADRS_RANGE_HIGH_ADDRESS_SHIFT        0
#define BCHP_MEMC_GEN_0_ARC_3_ADRS_RANGE_HIGH_ADDRESS_DEFAULT      0

/***************************************************************************
 *ARC_3_READ_RIGHTS_0 - Read access right of SCB clients 0 to 31 on Address Range Checker (ARC)-3
 ***************************************************************************/
/* MEMC_GEN_0 :: ARC_3_READ_RIGHTS_0 :: ACCESS_RIGHT [31:00] */
#define BCHP_MEMC_GEN_0_ARC_3_READ_RIGHTS_0_ACCESS_RIGHT_MASK      0xffffffff
#define BCHP_MEMC_GEN_0_ARC_3_READ_RIGHTS_0_ACCESS_RIGHT_SHIFT     0
#define BCHP_MEMC_GEN_0_ARC_3_READ_RIGHTS_0_ACCESS_RIGHT_DEFAULT   0

/***************************************************************************
 *ARC_3_READ_RIGHTS_1 - Read access right of SCB clients 32 to 63 on Address Range Checker(ARC)-3
 ***************************************************************************/
/* MEMC_GEN_0 :: ARC_3_READ_RIGHTS_1 :: ACCESS_RIGHT [31:00] */
#define BCHP_MEMC_GEN_0_ARC_3_READ_RIGHTS_1_ACCESS_RIGHT_MASK      0xffffffff
#define BCHP_MEMC_GEN_0_ARC_3_READ_RIGHTS_1_ACCESS_RIGHT_SHIFT     0
#define BCHP_MEMC_GEN_0_ARC_3_READ_RIGHTS_1_ACCESS_RIGHT_DEFAULT   0

/***************************************************************************
 *ARC_3_READ_RIGHTS_2 - Read access right of SCB clients 64 to 95 on Address Range Checker (ARC)-3
 ***************************************************************************/
/* MEMC_GEN_0 :: ARC_3_READ_RIGHTS_2 :: ACCESS_RIGHT [31:00] */
#define BCHP_MEMC_GEN_0_ARC_3_READ_RIGHTS_2_ACCESS_RIGHT_MASK      0xffffffff
#define BCHP_MEMC_GEN_0_ARC_3_READ_RIGHTS_2_ACCESS_RIGHT_SHIFT     0
#define BCHP_MEMC_GEN_0_ARC_3_READ_RIGHTS_2_ACCESS_RIGHT_DEFAULT   0

/***************************************************************************
 *ARC_3_READ_RIGHTS_3 - Read access right of SCB clients 96 to 127 on Address Range Checker(ARC)-3
 ***************************************************************************/
/* MEMC_GEN_0 :: ARC_3_READ_RIGHTS_3 :: ACCESS_RIGHT [31:00] */
#define BCHP_MEMC_GEN_0_ARC_3_READ_RIGHTS_3_ACCESS_RIGHT_MASK      0xffffffff
#define BCHP_MEMC_GEN_0_ARC_3_READ_RIGHTS_3_ACCESS_RIGHT_SHIFT     0
#define BCHP_MEMC_GEN_0_ARC_3_READ_RIGHTS_3_ACCESS_RIGHT_DEFAULT   0

/***************************************************************************
 *ARC_3_WRITE_RIGHTS_0 - Write access right of SCB clients 0 to 31 on Address Range Checker(ARC)-3
 ***************************************************************************/
/* MEMC_GEN_0 :: ARC_3_WRITE_RIGHTS_0 :: ACCESS_RIGHT [31:00] */
#define BCHP_MEMC_GEN_0_ARC_3_WRITE_RIGHTS_0_ACCESS_RIGHT_MASK     0xffffffff
#define BCHP_MEMC_GEN_0_ARC_3_WRITE_RIGHTS_0_ACCESS_RIGHT_SHIFT    0
#define BCHP_MEMC_GEN_0_ARC_3_WRITE_RIGHTS_0_ACCESS_RIGHT_DEFAULT  0

/***************************************************************************
 *ARC_3_WRITE_RIGHTS_1 - Write access right of SCB clients 32 to 63 on Address Range Checker(ARC)-3
 ***************************************************************************/
/* MEMC_GEN_0 :: ARC_3_WRITE_RIGHTS_1 :: ACCESS_RIGHT [31:00] */
#define BCHP_MEMC_GEN_0_ARC_3_WRITE_RIGHTS_1_ACCESS_RIGHT_MASK     0xffffffff
#define BCHP_MEMC_GEN_0_ARC_3_WRITE_RIGHTS_1_ACCESS_RIGHT_SHIFT    0
#define BCHP_MEMC_GEN_0_ARC_3_WRITE_RIGHTS_1_ACCESS_RIGHT_DEFAULT  0

/***************************************************************************
 *ARC_3_WRITE_RIGHTS_2 - Write access right of SCB clients 0 to 31 on Address Range Checker(ARC)-3
 ***************************************************************************/
/* MEMC_GEN_0 :: ARC_3_WRITE_RIGHTS_2 :: ACCESS_RIGHT [31:00] */
#define BCHP_MEMC_GEN_0_ARC_3_WRITE_RIGHTS_2_ACCESS_RIGHT_MASK     0xffffffff
#define BCHP_MEMC_GEN_0_ARC_3_WRITE_RIGHTS_2_ACCESS_RIGHT_SHIFT    0
#define BCHP_MEMC_GEN_0_ARC_3_WRITE_RIGHTS_2_ACCESS_RIGHT_DEFAULT  0

/***************************************************************************
 *ARC_3_WRITE_RIGHTS_3 - Write access right of SCB clients 32 to 63 on Address Range Checker(ARC)-3
 ***************************************************************************/
/* MEMC_GEN_0 :: ARC_3_WRITE_RIGHTS_3 :: ACCESS_RIGHT [31:00] */
#define BCHP_MEMC_GEN_0_ARC_3_WRITE_RIGHTS_3_ACCESS_RIGHT_MASK     0xffffffff
#define BCHP_MEMC_GEN_0_ARC_3_WRITE_RIGHTS_3_ACCESS_RIGHT_SHIFT    0
#define BCHP_MEMC_GEN_0_ARC_3_WRITE_RIGHTS_3_ACCESS_RIGHT_DEFAULT  0

/***************************************************************************
 *ARC_3_VIOLATION_INFO_START_ADDR - Violating Command Start Address for Address Range Checker (ARC)-3 .
 ***************************************************************************/
/* MEMC_GEN_0 :: ARC_3_VIOLATION_INFO_START_ADDR :: reserved0 [31:29] */
#define BCHP_MEMC_GEN_0_ARC_3_VIOLATION_INFO_START_ADDR_reserved0_MASK 0xe0000000
#define BCHP_MEMC_GEN_0_ARC_3_VIOLATION_INFO_START_ADDR_reserved0_SHIFT 29

/* MEMC_GEN_0 :: ARC_3_VIOLATION_INFO_START_ADDR :: ADDRESS [28:00] */
#define BCHP_MEMC_GEN_0_ARC_3_VIOLATION_INFO_START_ADDR_ADDRESS_MASK 0x1fffffff
#define BCHP_MEMC_GEN_0_ARC_3_VIOLATION_INFO_START_ADDR_ADDRESS_SHIFT 0
#define BCHP_MEMC_GEN_0_ARC_3_VIOLATION_INFO_START_ADDR_ADDRESS_DEFAULT 0

/***************************************************************************
 *ARC_3_VIOLATION_INFO_END_ADDR - Violating Command End Address for Address Range Checker (ARC)-3 .
 ***************************************************************************/
/* MEMC_GEN_0 :: ARC_3_VIOLATION_INFO_END_ADDR :: reserved0 [31:29] */
#define BCHP_MEMC_GEN_0_ARC_3_VIOLATION_INFO_END_ADDR_reserved0_MASK 0xe0000000
#define BCHP_MEMC_GEN_0_ARC_3_VIOLATION_INFO_END_ADDR_reserved0_SHIFT 29

/* MEMC_GEN_0 :: ARC_3_VIOLATION_INFO_END_ADDR :: ADDRESS [28:00] */
#define BCHP_MEMC_GEN_0_ARC_3_VIOLATION_INFO_END_ADDR_ADDRESS_MASK 0x1fffffff
#define BCHP_MEMC_GEN_0_ARC_3_VIOLATION_INFO_END_ADDR_ADDRESS_SHIFT 0
#define BCHP_MEMC_GEN_0_ARC_3_VIOLATION_INFO_END_ADDR_ADDRESS_DEFAULT 0

/***************************************************************************
 *ARC_3_VIOLATION_INFO_CMD - Violating SCB client-ID & Command Type for Address Range Checker (ARC)-3 .
 ***************************************************************************/
/* MEMC_GEN_0 :: ARC_3_VIOLATION_INFO_CMD :: reserved0 [31:31] */
#define BCHP_MEMC_GEN_0_ARC_3_VIOLATION_INFO_CMD_reserved0_MASK    0x80000000
#define BCHP_MEMC_GEN_0_ARC_3_VIOLATION_INFO_CMD_reserved0_SHIFT   31

/* MEMC_GEN_0 :: ARC_3_VIOLATION_INFO_CMD :: CLIENTID [30:24] */
#define BCHP_MEMC_GEN_0_ARC_3_VIOLATION_INFO_CMD_CLIENTID_MASK     0x7f000000
#define BCHP_MEMC_GEN_0_ARC_3_VIOLATION_INFO_CMD_CLIENTID_SHIFT    24
#define BCHP_MEMC_GEN_0_ARC_3_VIOLATION_INFO_CMD_CLIENTID_DEFAULT  0

/* MEMC_GEN_0 :: ARC_3_VIOLATION_INFO_CMD :: reserved1 [23:22] */
#define BCHP_MEMC_GEN_0_ARC_3_VIOLATION_INFO_CMD_reserved1_MASK    0x00c00000
#define BCHP_MEMC_GEN_0_ARC_3_VIOLATION_INFO_CMD_reserved1_SHIFT   22

/* MEMC_GEN_0 :: ARC_3_VIOLATION_INFO_CMD :: NMB [21:12] */
#define BCHP_MEMC_GEN_0_ARC_3_VIOLATION_INFO_CMD_NMB_MASK          0x003ff000
#define BCHP_MEMC_GEN_0_ARC_3_VIOLATION_INFO_CMD_NMB_SHIFT         12
#define BCHP_MEMC_GEN_0_ARC_3_VIOLATION_INFO_CMD_NMB_DEFAULT       0

/* MEMC_GEN_0 :: ARC_3_VIOLATION_INFO_CMD :: reserved2 [11:09] */
#define BCHP_MEMC_GEN_0_ARC_3_VIOLATION_INFO_CMD_reserved2_MASK    0x00000e00
#define BCHP_MEMC_GEN_0_ARC_3_VIOLATION_INFO_CMD_reserved2_SHIFT   9

/* MEMC_GEN_0 :: ARC_3_VIOLATION_INFO_CMD :: REQ_TYPE [08:00] */
#define BCHP_MEMC_GEN_0_ARC_3_VIOLATION_INFO_CMD_REQ_TYPE_MASK     0x000001ff
#define BCHP_MEMC_GEN_0_ARC_3_VIOLATION_INFO_CMD_REQ_TYPE_SHIFT    0
#define BCHP_MEMC_GEN_0_ARC_3_VIOLATION_INFO_CMD_REQ_TYPE_DEFAULT  0

/***************************************************************************
 *ARC_3_VIOLATION_INFO_CLEAR - ARCH3 violation info write clear register
 ***************************************************************************/
/* MEMC_GEN_0 :: ARC_3_VIOLATION_INFO_CLEAR :: reserved0 [31:01] */
#define BCHP_MEMC_GEN_0_ARC_3_VIOLATION_INFO_CLEAR_reserved0_MASK  0xfffffffe
#define BCHP_MEMC_GEN_0_ARC_3_VIOLATION_INFO_CLEAR_reserved0_SHIFT 1

/* MEMC_GEN_0 :: ARC_3_VIOLATION_INFO_CLEAR :: WRITE_CLEAR [00:00] */
#define BCHP_MEMC_GEN_0_ARC_3_VIOLATION_INFO_CLEAR_WRITE_CLEAR_MASK 0x00000001
#define BCHP_MEMC_GEN_0_ARC_3_VIOLATION_INFO_CLEAR_WRITE_CLEAR_SHIFT 0
#define BCHP_MEMC_GEN_0_ARC_3_VIOLATION_INFO_CLEAR_WRITE_CLEAR_DEFAULT 0

/***************************************************************************
 *MEMC64_MBIST_TM_CNTRL - MEMC64_0 MBIST TM Control Register
 ***************************************************************************/
/* MEMC_GEN_0 :: MEMC64_MBIST_TM_CNTRL :: reserved0 [31:10] */
#define BCHP_MEMC_GEN_0_MEMC64_MBIST_TM_CNTRL_reserved0_MASK       0xfffffc00
#define BCHP_MEMC_GEN_0_MEMC64_MBIST_TM_CNTRL_reserved0_SHIFT      10

/* MEMC_GEN_0 :: MEMC64_MBIST_TM_CNTRL :: MEMC_0_RD_FIFO_1 [09:08] */
#define BCHP_MEMC_GEN_0_MEMC64_MBIST_TM_CNTRL_MEMC_0_RD_FIFO_1_MASK 0x00000300
#define BCHP_MEMC_GEN_0_MEMC64_MBIST_TM_CNTRL_MEMC_0_RD_FIFO_1_SHIFT 8
#define BCHP_MEMC_GEN_0_MEMC64_MBIST_TM_CNTRL_MEMC_0_RD_FIFO_1_DEFAULT 0

/* MEMC_GEN_0 :: MEMC64_MBIST_TM_CNTRL :: MEMC_0_RD_FIFO_0 [07:06] */
#define BCHP_MEMC_GEN_0_MEMC64_MBIST_TM_CNTRL_MEMC_0_RD_FIFO_0_MASK 0x000000c0
#define BCHP_MEMC_GEN_0_MEMC64_MBIST_TM_CNTRL_MEMC_0_RD_FIFO_0_SHIFT 6
#define BCHP_MEMC_GEN_0_MEMC64_MBIST_TM_CNTRL_MEMC_0_RD_FIFO_0_DEFAULT 0

/* MEMC_GEN_0 :: MEMC64_MBIST_TM_CNTRL :: MEMC_0_WR_FIFO_2 [05:04] */
#define BCHP_MEMC_GEN_0_MEMC64_MBIST_TM_CNTRL_MEMC_0_WR_FIFO_2_MASK 0x00000030
#define BCHP_MEMC_GEN_0_MEMC64_MBIST_TM_CNTRL_MEMC_0_WR_FIFO_2_SHIFT 4
#define BCHP_MEMC_GEN_0_MEMC64_MBIST_TM_CNTRL_MEMC_0_WR_FIFO_2_DEFAULT 0

/* MEMC_GEN_0 :: MEMC64_MBIST_TM_CNTRL :: MEMC_0_WR_FIFO_1 [03:02] */
#define BCHP_MEMC_GEN_0_MEMC64_MBIST_TM_CNTRL_MEMC_0_WR_FIFO_1_MASK 0x0000000c
#define BCHP_MEMC_GEN_0_MEMC64_MBIST_TM_CNTRL_MEMC_0_WR_FIFO_1_SHIFT 2
#define BCHP_MEMC_GEN_0_MEMC64_MBIST_TM_CNTRL_MEMC_0_WR_FIFO_1_DEFAULT 0

/* MEMC_GEN_0 :: MEMC64_MBIST_TM_CNTRL :: MEMC_0_WR_FIFO_0 [01:00] */
#define BCHP_MEMC_GEN_0_MEMC64_MBIST_TM_CNTRL_MEMC_0_WR_FIFO_0_MASK 0x00000003
#define BCHP_MEMC_GEN_0_MEMC64_MBIST_TM_CNTRL_MEMC_0_WR_FIFO_0_SHIFT 0
#define BCHP_MEMC_GEN_0_MEMC64_MBIST_TM_CNTRL_MEMC_0_WR_FIFO_0_DEFAULT 0

/***************************************************************************
 *DUMMY_CMD - Dummy SCB Command
 ***************************************************************************/
/* MEMC_GEN_0 :: DUMMY_CMD :: reserved0 [31:09] */
#define BCHP_MEMC_GEN_0_DUMMY_CMD_reserved0_MASK                   0xfffffe00
#define BCHP_MEMC_GEN_0_DUMMY_CMD_reserved0_SHIFT                  9

/* MEMC_GEN_0 :: DUMMY_CMD :: CMD [08:00] */
#define BCHP_MEMC_GEN_0_DUMMY_CMD_CMD_MASK                         0x000001ff
#define BCHP_MEMC_GEN_0_DUMMY_CMD_CMD_SHIFT                        0
#define BCHP_MEMC_GEN_0_DUMMY_CMD_CMD_DEFAULT                      95

/***************************************************************************
 *DUMMY_REQ_CNT_CPU0 - Dummy Request Count CPU0
 ***************************************************************************/
/* MEMC_GEN_0 :: DUMMY_REQ_CNT_CPU0 :: COUNT [31:00] */
#define BCHP_MEMC_GEN_0_DUMMY_REQ_CNT_CPU0_COUNT_MASK              0xffffffff
#define BCHP_MEMC_GEN_0_DUMMY_REQ_CNT_CPU0_COUNT_SHIFT             0
#define BCHP_MEMC_GEN_0_DUMMY_REQ_CNT_CPU0_COUNT_DEFAULT           0

/***************************************************************************
 *DUMMY_REQ_CNT_CPU1 - Dummy Request Count CPU1
 ***************************************************************************/
/* MEMC_GEN_0 :: DUMMY_REQ_CNT_CPU1 :: COUNT [31:00] */
#define BCHP_MEMC_GEN_0_DUMMY_REQ_CNT_CPU1_COUNT_MASK              0xffffffff
#define BCHP_MEMC_GEN_0_DUMMY_REQ_CNT_CPU1_COUNT_SHIFT             0
#define BCHP_MEMC_GEN_0_DUMMY_REQ_CNT_CPU1_COUNT_DEFAULT           0

/***************************************************************************
 *CNTR_RST - Reset Request Counters
 ***************************************************************************/
/* MEMC_GEN_0 :: CNTR_RST :: reserved0 [31:04] */
#define BCHP_MEMC_GEN_0_CNTR_RST_reserved0_MASK                    0xfffffff0
#define BCHP_MEMC_GEN_0_CNTR_RST_reserved0_SHIFT                   4

/* MEMC_GEN_0 :: CNTR_RST :: RST_DUMMY_REQ_CNT_CPU1 [03:03] */
#define BCHP_MEMC_GEN_0_CNTR_RST_RST_DUMMY_REQ_CNT_CPU1_MASK       0x00000008
#define BCHP_MEMC_GEN_0_CNTR_RST_RST_DUMMY_REQ_CNT_CPU1_SHIFT      3
#define BCHP_MEMC_GEN_0_CNTR_RST_RST_DUMMY_REQ_CNT_CPU1_DEFAULT    0

/* MEMC_GEN_0 :: CNTR_RST :: RST_DUMMY_REQ_CNT_CPU0 [02:02] */
#define BCHP_MEMC_GEN_0_CNTR_RST_RST_DUMMY_REQ_CNT_CPU0_MASK       0x00000004
#define BCHP_MEMC_GEN_0_CNTR_RST_RST_DUMMY_REQ_CNT_CPU0_SHIFT      2
#define BCHP_MEMC_GEN_0_CNTR_RST_RST_DUMMY_REQ_CNT_CPU0_DEFAULT    0

/* MEMC_GEN_0 :: CNTR_RST :: RST_VAL_REQ_CNT_CPU1 [01:01] */
#define BCHP_MEMC_GEN_0_CNTR_RST_RST_VAL_REQ_CNT_CPU1_MASK         0x00000002
#define BCHP_MEMC_GEN_0_CNTR_RST_RST_VAL_REQ_CNT_CPU1_SHIFT        1
#define BCHP_MEMC_GEN_0_CNTR_RST_RST_VAL_REQ_CNT_CPU1_DEFAULT      0

/* MEMC_GEN_0 :: CNTR_RST :: RST_VAL_REQ_CNT_CPU0 [00:00] */
#define BCHP_MEMC_GEN_0_CNTR_RST_RST_VAL_REQ_CNT_CPU0_MASK         0x00000001
#define BCHP_MEMC_GEN_0_CNTR_RST_RST_VAL_REQ_CNT_CPU0_SHIFT        0
#define BCHP_MEMC_GEN_0_CNTR_RST_RST_VAL_REQ_CNT_CPU0_DEFAULT      0

/***************************************************************************
 *CNTR_FREEZE - Freeze Request Counters
 ***************************************************************************/
/* MEMC_GEN_0 :: CNTR_FREEZE :: reserved0 [31:04] */
#define BCHP_MEMC_GEN_0_CNTR_FREEZE_reserved0_MASK                 0xfffffff0
#define BCHP_MEMC_GEN_0_CNTR_FREEZE_reserved0_SHIFT                4

/* MEMC_GEN_0 :: CNTR_FREEZE :: FRZ_DUMMY_REQ_CNT_CPU1 [03:03] */
#define BCHP_MEMC_GEN_0_CNTR_FREEZE_FRZ_DUMMY_REQ_CNT_CPU1_MASK    0x00000008
#define BCHP_MEMC_GEN_0_CNTR_FREEZE_FRZ_DUMMY_REQ_CNT_CPU1_SHIFT   3
#define BCHP_MEMC_GEN_0_CNTR_FREEZE_FRZ_DUMMY_REQ_CNT_CPU1_DEFAULT 0

/* MEMC_GEN_0 :: CNTR_FREEZE :: FRZ_DUMMY_REQ_CNT_CPU0 [02:02] */
#define BCHP_MEMC_GEN_0_CNTR_FREEZE_FRZ_DUMMY_REQ_CNT_CPU0_MASK    0x00000004
#define BCHP_MEMC_GEN_0_CNTR_FREEZE_FRZ_DUMMY_REQ_CNT_CPU0_SHIFT   2
#define BCHP_MEMC_GEN_0_CNTR_FREEZE_FRZ_DUMMY_REQ_CNT_CPU0_DEFAULT 0

/* MEMC_GEN_0 :: CNTR_FREEZE :: FRZ_VAL_REQ_CNT_CPU1 [01:01] */
#define BCHP_MEMC_GEN_0_CNTR_FREEZE_FRZ_VAL_REQ_CNT_CPU1_MASK      0x00000002
#define BCHP_MEMC_GEN_0_CNTR_FREEZE_FRZ_VAL_REQ_CNT_CPU1_SHIFT     1
#define BCHP_MEMC_GEN_0_CNTR_FREEZE_FRZ_VAL_REQ_CNT_CPU1_DEFAULT   0

/* MEMC_GEN_0 :: CNTR_FREEZE :: FRZ_VAL_REQ_CNT_CPU0 [00:00] */
#define BCHP_MEMC_GEN_0_CNTR_FREEZE_FRZ_VAL_REQ_CNT_CPU0_MASK      0x00000001
#define BCHP_MEMC_GEN_0_CNTR_FREEZE_FRZ_VAL_REQ_CNT_CPU0_SHIFT     0
#define BCHP_MEMC_GEN_0_CNTR_FREEZE_FRZ_VAL_REQ_CNT_CPU0_DEFAULT   0

/***************************************************************************
 *VAL_REQ_CNT_CPU0 - Valid Request Count CPU0
 ***************************************************************************/
/* MEMC_GEN_0 :: VAL_REQ_CNT_CPU0 :: COUNT [31:00] */
#define BCHP_MEMC_GEN_0_VAL_REQ_CNT_CPU0_COUNT_MASK                0xffffffff
#define BCHP_MEMC_GEN_0_VAL_REQ_CNT_CPU0_COUNT_SHIFT               0
#define BCHP_MEMC_GEN_0_VAL_REQ_CNT_CPU0_COUNT_DEFAULT             0

/***************************************************************************
 *VAL_REQ_CNT_CPU1 - Valid Request Count CPU1
 ***************************************************************************/
/* MEMC_GEN_0 :: VAL_REQ_CNT_CPU1 :: COUNT [31:00] */
#define BCHP_MEMC_GEN_0_VAL_REQ_CNT_CPU1_COUNT_MASK                0xffffffff
#define BCHP_MEMC_GEN_0_VAL_REQ_CNT_CPU1_COUNT_SHIFT               0
#define BCHP_MEMC_GEN_0_VAL_REQ_CNT_CPU1_COUNT_DEFAULT             0

/***************************************************************************
 *PFRI_0_PAGE_BRK_INTR_INFO_0 - PFRI Page Break Interrupt Information Register 0 for lient 120
 ***************************************************************************/
/* MEMC_GEN_0 :: PFRI_0_PAGE_BRK_INTR_INFO_0 :: reserved0 [31:20] */
#define BCHP_MEMC_GEN_0_PFRI_0_PAGE_BRK_INTR_INFO_0_reserved0_MASK 0xfff00000
#define BCHP_MEMC_GEN_0_PFRI_0_PAGE_BRK_INTR_INFO_0_reserved0_SHIFT 20

/* MEMC_GEN_0 :: PFRI_0_PAGE_BRK_INTR_INFO_0 :: BANK_ADDRESS [19:17] */
#define BCHP_MEMC_GEN_0_PFRI_0_PAGE_BRK_INTR_INFO_0_BANK_ADDRESS_MASK 0x000e0000
#define BCHP_MEMC_GEN_0_PFRI_0_PAGE_BRK_INTR_INFO_0_BANK_ADDRESS_SHIFT 17
#define BCHP_MEMC_GEN_0_PFRI_0_PAGE_BRK_INTR_INFO_0_BANK_ADDRESS_DEFAULT 0

/* MEMC_GEN_0 :: PFRI_0_PAGE_BRK_INTR_INFO_0 :: reserved1 [16:16] */
#define BCHP_MEMC_GEN_0_PFRI_0_PAGE_BRK_INTR_INFO_0_reserved1_MASK 0x00010000
#define BCHP_MEMC_GEN_0_PFRI_0_PAGE_BRK_INTR_INFO_0_reserved1_SHIFT 16

/* MEMC_GEN_0 :: PFRI_0_PAGE_BRK_INTR_INFO_0 :: ROW_ADDRESS [15:00] */
#define BCHP_MEMC_GEN_0_PFRI_0_PAGE_BRK_INTR_INFO_0_ROW_ADDRESS_MASK 0x0000ffff
#define BCHP_MEMC_GEN_0_PFRI_0_PAGE_BRK_INTR_INFO_0_ROW_ADDRESS_SHIFT 0
#define BCHP_MEMC_GEN_0_PFRI_0_PAGE_BRK_INTR_INFO_0_ROW_ADDRESS_DEFAULT 0

/***************************************************************************
 *PFRI_0_PAGE_BRK_INTR_INFO_1 - PFRI Page Break Interrupt Information Register 1 for client 120
 ***************************************************************************/
/* MEMC_GEN_0 :: PFRI_0_PAGE_BRK_INTR_INFO_1 :: reserved0 [31:20] */
#define BCHP_MEMC_GEN_0_PFRI_0_PAGE_BRK_INTR_INFO_1_reserved0_MASK 0xfff00000
#define BCHP_MEMC_GEN_0_PFRI_0_PAGE_BRK_INTR_INFO_1_reserved0_SHIFT 20

/* MEMC_GEN_0 :: PFRI_0_PAGE_BRK_INTR_INFO_1 :: BANK_ADDRESS [19:17] */
#define BCHP_MEMC_GEN_0_PFRI_0_PAGE_BRK_INTR_INFO_1_BANK_ADDRESS_MASK 0x000e0000
#define BCHP_MEMC_GEN_0_PFRI_0_PAGE_BRK_INTR_INFO_1_BANK_ADDRESS_SHIFT 17
#define BCHP_MEMC_GEN_0_PFRI_0_PAGE_BRK_INTR_INFO_1_BANK_ADDRESS_DEFAULT 0

/* MEMC_GEN_0 :: PFRI_0_PAGE_BRK_INTR_INFO_1 :: reserved1 [16:16] */
#define BCHP_MEMC_GEN_0_PFRI_0_PAGE_BRK_INTR_INFO_1_reserved1_MASK 0x00010000
#define BCHP_MEMC_GEN_0_PFRI_0_PAGE_BRK_INTR_INFO_1_reserved1_SHIFT 16

/* MEMC_GEN_0 :: PFRI_0_PAGE_BRK_INTR_INFO_1 :: ROW_ADDRESS [15:00] */
#define BCHP_MEMC_GEN_0_PFRI_0_PAGE_BRK_INTR_INFO_1_ROW_ADDRESS_MASK 0x0000ffff
#define BCHP_MEMC_GEN_0_PFRI_0_PAGE_BRK_INTR_INFO_1_ROW_ADDRESS_SHIFT 0
#define BCHP_MEMC_GEN_0_PFRI_0_PAGE_BRK_INTR_INFO_1_ROW_ADDRESS_DEFAULT 0

/***************************************************************************
 *PFRI_0_VIOLATION_INFO_WRITE_CLEAR - PFRI violation info write clear register for client 120
 ***************************************************************************/
/* MEMC_GEN_0 :: PFRI_0_VIOLATION_INFO_WRITE_CLEAR :: reserved0 [31:01] */
#define BCHP_MEMC_GEN_0_PFRI_0_VIOLATION_INFO_WRITE_CLEAR_reserved0_MASK 0xfffffffe
#define BCHP_MEMC_GEN_0_PFRI_0_VIOLATION_INFO_WRITE_CLEAR_reserved0_SHIFT 1

/* MEMC_GEN_0 :: PFRI_0_VIOLATION_INFO_WRITE_CLEAR :: WRITE_CLEAR [00:00] */
#define BCHP_MEMC_GEN_0_PFRI_0_VIOLATION_INFO_WRITE_CLEAR_WRITE_CLEAR_MASK 0x00000001
#define BCHP_MEMC_GEN_0_PFRI_0_VIOLATION_INFO_WRITE_CLEAR_WRITE_CLEAR_SHIFT 0
#define BCHP_MEMC_GEN_0_PFRI_0_VIOLATION_INFO_WRITE_CLEAR_WRITE_CLEAR_DEFAULT 0

/***************************************************************************
 *PFRI_1_PAGE_BRK_INTR_INFO_0 - PFRI Page Break Interrupt Information Register 0 for client 121
 ***************************************************************************/
/* MEMC_GEN_0 :: PFRI_1_PAGE_BRK_INTR_INFO_0 :: reserved0 [31:20] */
#define BCHP_MEMC_GEN_0_PFRI_1_PAGE_BRK_INTR_INFO_0_reserved0_MASK 0xfff00000
#define BCHP_MEMC_GEN_0_PFRI_1_PAGE_BRK_INTR_INFO_0_reserved0_SHIFT 20

/* MEMC_GEN_0 :: PFRI_1_PAGE_BRK_INTR_INFO_0 :: BANK_ADDRESS [19:17] */
#define BCHP_MEMC_GEN_0_PFRI_1_PAGE_BRK_INTR_INFO_0_BANK_ADDRESS_MASK 0x000e0000
#define BCHP_MEMC_GEN_0_PFRI_1_PAGE_BRK_INTR_INFO_0_BANK_ADDRESS_SHIFT 17
#define BCHP_MEMC_GEN_0_PFRI_1_PAGE_BRK_INTR_INFO_0_BANK_ADDRESS_DEFAULT 0

/* MEMC_GEN_0 :: PFRI_1_PAGE_BRK_INTR_INFO_0 :: reserved1 [16:16] */
#define BCHP_MEMC_GEN_0_PFRI_1_PAGE_BRK_INTR_INFO_0_reserved1_MASK 0x00010000
#define BCHP_MEMC_GEN_0_PFRI_1_PAGE_BRK_INTR_INFO_0_reserved1_SHIFT 16

/* MEMC_GEN_0 :: PFRI_1_PAGE_BRK_INTR_INFO_0 :: ROW_ADDRESS [15:00] */
#define BCHP_MEMC_GEN_0_PFRI_1_PAGE_BRK_INTR_INFO_0_ROW_ADDRESS_MASK 0x0000ffff
#define BCHP_MEMC_GEN_0_PFRI_1_PAGE_BRK_INTR_INFO_0_ROW_ADDRESS_SHIFT 0
#define BCHP_MEMC_GEN_0_PFRI_1_PAGE_BRK_INTR_INFO_0_ROW_ADDRESS_DEFAULT 0

/***************************************************************************
 *PFRI_1_PAGE_BRK_INTR_INFO_1 - PFRI Page Break Interrupt Information Register 1 for client 121
 ***************************************************************************/
/* MEMC_GEN_0 :: PFRI_1_PAGE_BRK_INTR_INFO_1 :: reserved0 [31:20] */
#define BCHP_MEMC_GEN_0_PFRI_1_PAGE_BRK_INTR_INFO_1_reserved0_MASK 0xfff00000
#define BCHP_MEMC_GEN_0_PFRI_1_PAGE_BRK_INTR_INFO_1_reserved0_SHIFT 20

/* MEMC_GEN_0 :: PFRI_1_PAGE_BRK_INTR_INFO_1 :: BANK_ADDRESS [19:17] */
#define BCHP_MEMC_GEN_0_PFRI_1_PAGE_BRK_INTR_INFO_1_BANK_ADDRESS_MASK 0x000e0000
#define BCHP_MEMC_GEN_0_PFRI_1_PAGE_BRK_INTR_INFO_1_BANK_ADDRESS_SHIFT 17
#define BCHP_MEMC_GEN_0_PFRI_1_PAGE_BRK_INTR_INFO_1_BANK_ADDRESS_DEFAULT 0

/* MEMC_GEN_0 :: PFRI_1_PAGE_BRK_INTR_INFO_1 :: reserved1 [16:16] */
#define BCHP_MEMC_GEN_0_PFRI_1_PAGE_BRK_INTR_INFO_1_reserved1_MASK 0x00010000
#define BCHP_MEMC_GEN_0_PFRI_1_PAGE_BRK_INTR_INFO_1_reserved1_SHIFT 16

/* MEMC_GEN_0 :: PFRI_1_PAGE_BRK_INTR_INFO_1 :: ROW_ADDRESS [15:00] */
#define BCHP_MEMC_GEN_0_PFRI_1_PAGE_BRK_INTR_INFO_1_ROW_ADDRESS_MASK 0x0000ffff
#define BCHP_MEMC_GEN_0_PFRI_1_PAGE_BRK_INTR_INFO_1_ROW_ADDRESS_SHIFT 0
#define BCHP_MEMC_GEN_0_PFRI_1_PAGE_BRK_INTR_INFO_1_ROW_ADDRESS_DEFAULT 0

/***************************************************************************
 *PFRI_1_VIOLATION_INFO_WRITE_CLEAR - PFRI violation info write clear register for client 121
 ***************************************************************************/
/* MEMC_GEN_0 :: PFRI_1_VIOLATION_INFO_WRITE_CLEAR :: reserved0 [31:01] */
#define BCHP_MEMC_GEN_0_PFRI_1_VIOLATION_INFO_WRITE_CLEAR_reserved0_MASK 0xfffffffe
#define BCHP_MEMC_GEN_0_PFRI_1_VIOLATION_INFO_WRITE_CLEAR_reserved0_SHIFT 1

/* MEMC_GEN_0 :: PFRI_1_VIOLATION_INFO_WRITE_CLEAR :: WRITE_CLEAR [00:00] */
#define BCHP_MEMC_GEN_0_PFRI_1_VIOLATION_INFO_WRITE_CLEAR_WRITE_CLEAR_MASK 0x00000001
#define BCHP_MEMC_GEN_0_PFRI_1_VIOLATION_INFO_WRITE_CLEAR_WRITE_CLEAR_SHIFT 0
#define BCHP_MEMC_GEN_0_PFRI_1_VIOLATION_INFO_WRITE_CLEAR_WRITE_CLEAR_DEFAULT 0

/***************************************************************************
 *PFRI_2_PAGE_BRK_INTR_INFO_0 - PFRI Page Break Interrupt Information Register 0 for client 122
 ***************************************************************************/
/* MEMC_GEN_0 :: PFRI_2_PAGE_BRK_INTR_INFO_0 :: reserved0 [31:20] */
#define BCHP_MEMC_GEN_0_PFRI_2_PAGE_BRK_INTR_INFO_0_reserved0_MASK 0xfff00000
#define BCHP_MEMC_GEN_0_PFRI_2_PAGE_BRK_INTR_INFO_0_reserved0_SHIFT 20

/* MEMC_GEN_0 :: PFRI_2_PAGE_BRK_INTR_INFO_0 :: BANK_ADDRESS [19:17] */
#define BCHP_MEMC_GEN_0_PFRI_2_PAGE_BRK_INTR_INFO_0_BANK_ADDRESS_MASK 0x000e0000
#define BCHP_MEMC_GEN_0_PFRI_2_PAGE_BRK_INTR_INFO_0_BANK_ADDRESS_SHIFT 17
#define BCHP_MEMC_GEN_0_PFRI_2_PAGE_BRK_INTR_INFO_0_BANK_ADDRESS_DEFAULT 0

/* MEMC_GEN_0 :: PFRI_2_PAGE_BRK_INTR_INFO_0 :: reserved1 [16:16] */
#define BCHP_MEMC_GEN_0_PFRI_2_PAGE_BRK_INTR_INFO_0_reserved1_MASK 0x00010000
#define BCHP_MEMC_GEN_0_PFRI_2_PAGE_BRK_INTR_INFO_0_reserved1_SHIFT 16

/* MEMC_GEN_0 :: PFRI_2_PAGE_BRK_INTR_INFO_0 :: ROW_ADDRESS [15:00] */
#define BCHP_MEMC_GEN_0_PFRI_2_PAGE_BRK_INTR_INFO_0_ROW_ADDRESS_MASK 0x0000ffff
#define BCHP_MEMC_GEN_0_PFRI_2_PAGE_BRK_INTR_INFO_0_ROW_ADDRESS_SHIFT 0
#define BCHP_MEMC_GEN_0_PFRI_2_PAGE_BRK_INTR_INFO_0_ROW_ADDRESS_DEFAULT 0

/***************************************************************************
 *PFRI_2_PAGE_BRK_INTR_INFO_1 - PFRI Page Break Interrupt Information Register 1 for client 122
 ***************************************************************************/
/* MEMC_GEN_0 :: PFRI_2_PAGE_BRK_INTR_INFO_1 :: reserved0 [31:20] */
#define BCHP_MEMC_GEN_0_PFRI_2_PAGE_BRK_INTR_INFO_1_reserved0_MASK 0xfff00000
#define BCHP_MEMC_GEN_0_PFRI_2_PAGE_BRK_INTR_INFO_1_reserved0_SHIFT 20

/* MEMC_GEN_0 :: PFRI_2_PAGE_BRK_INTR_INFO_1 :: BANK_ADDRESS [19:17] */
#define BCHP_MEMC_GEN_0_PFRI_2_PAGE_BRK_INTR_INFO_1_BANK_ADDRESS_MASK 0x000e0000
#define BCHP_MEMC_GEN_0_PFRI_2_PAGE_BRK_INTR_INFO_1_BANK_ADDRESS_SHIFT 17
#define BCHP_MEMC_GEN_0_PFRI_2_PAGE_BRK_INTR_INFO_1_BANK_ADDRESS_DEFAULT 0

/* MEMC_GEN_0 :: PFRI_2_PAGE_BRK_INTR_INFO_1 :: reserved1 [16:16] */
#define BCHP_MEMC_GEN_0_PFRI_2_PAGE_BRK_INTR_INFO_1_reserved1_MASK 0x00010000
#define BCHP_MEMC_GEN_0_PFRI_2_PAGE_BRK_INTR_INFO_1_reserved1_SHIFT 16

/* MEMC_GEN_0 :: PFRI_2_PAGE_BRK_INTR_INFO_1 :: ROW_ADDRESS [15:00] */
#define BCHP_MEMC_GEN_0_PFRI_2_PAGE_BRK_INTR_INFO_1_ROW_ADDRESS_MASK 0x0000ffff
#define BCHP_MEMC_GEN_0_PFRI_2_PAGE_BRK_INTR_INFO_1_ROW_ADDRESS_SHIFT 0
#define BCHP_MEMC_GEN_0_PFRI_2_PAGE_BRK_INTR_INFO_1_ROW_ADDRESS_DEFAULT 0

/***************************************************************************
 *PFRI_2_VIOLATION_INFO_WRITE_CLEAR - PFRI violation info write clear register client 122
 ***************************************************************************/
/* MEMC_GEN_0 :: PFRI_2_VIOLATION_INFO_WRITE_CLEAR :: reserved0 [31:01] */
#define BCHP_MEMC_GEN_0_PFRI_2_VIOLATION_INFO_WRITE_CLEAR_reserved0_MASK 0xfffffffe
#define BCHP_MEMC_GEN_0_PFRI_2_VIOLATION_INFO_WRITE_CLEAR_reserved0_SHIFT 1

/* MEMC_GEN_0 :: PFRI_2_VIOLATION_INFO_WRITE_CLEAR :: WRITE_CLEAR [00:00] */
#define BCHP_MEMC_GEN_0_PFRI_2_VIOLATION_INFO_WRITE_CLEAR_WRITE_CLEAR_MASK 0x00000001
#define BCHP_MEMC_GEN_0_PFRI_2_VIOLATION_INFO_WRITE_CLEAR_WRITE_CLEAR_SHIFT 0
#define BCHP_MEMC_GEN_0_PFRI_2_VIOLATION_INFO_WRITE_CLEAR_WRITE_CLEAR_DEFAULT 0

/***************************************************************************
 *PFRI_3_PAGE_BRK_INTR_INFO_0 - PFRI Page Break Interrupt Information Register 0 for client 123
 ***************************************************************************/
/* MEMC_GEN_0 :: PFRI_3_PAGE_BRK_INTR_INFO_0 :: reserved0 [31:20] */
#define BCHP_MEMC_GEN_0_PFRI_3_PAGE_BRK_INTR_INFO_0_reserved0_MASK 0xfff00000
#define BCHP_MEMC_GEN_0_PFRI_3_PAGE_BRK_INTR_INFO_0_reserved0_SHIFT 20

/* MEMC_GEN_0 :: PFRI_3_PAGE_BRK_INTR_INFO_0 :: BANK_ADDRESS [19:17] */
#define BCHP_MEMC_GEN_0_PFRI_3_PAGE_BRK_INTR_INFO_0_BANK_ADDRESS_MASK 0x000e0000
#define BCHP_MEMC_GEN_0_PFRI_3_PAGE_BRK_INTR_INFO_0_BANK_ADDRESS_SHIFT 17
#define BCHP_MEMC_GEN_0_PFRI_3_PAGE_BRK_INTR_INFO_0_BANK_ADDRESS_DEFAULT 0

/* MEMC_GEN_0 :: PFRI_3_PAGE_BRK_INTR_INFO_0 :: reserved1 [16:16] */
#define BCHP_MEMC_GEN_0_PFRI_3_PAGE_BRK_INTR_INFO_0_reserved1_MASK 0x00010000
#define BCHP_MEMC_GEN_0_PFRI_3_PAGE_BRK_INTR_INFO_0_reserved1_SHIFT 16

/* MEMC_GEN_0 :: PFRI_3_PAGE_BRK_INTR_INFO_0 :: ROW_ADDRESS [15:00] */
#define BCHP_MEMC_GEN_0_PFRI_3_PAGE_BRK_INTR_INFO_0_ROW_ADDRESS_MASK 0x0000ffff
#define BCHP_MEMC_GEN_0_PFRI_3_PAGE_BRK_INTR_INFO_0_ROW_ADDRESS_SHIFT 0
#define BCHP_MEMC_GEN_0_PFRI_3_PAGE_BRK_INTR_INFO_0_ROW_ADDRESS_DEFAULT 0

/***************************************************************************
 *PFRI_3_PAGE_BRK_INTR_INFO_1 - PFRI Page Break Interrupt Information Register 1 for client 123
 ***************************************************************************/
/* MEMC_GEN_0 :: PFRI_3_PAGE_BRK_INTR_INFO_1 :: reserved0 [31:20] */
#define BCHP_MEMC_GEN_0_PFRI_3_PAGE_BRK_INTR_INFO_1_reserved0_MASK 0xfff00000
#define BCHP_MEMC_GEN_0_PFRI_3_PAGE_BRK_INTR_INFO_1_reserved0_SHIFT 20

/* MEMC_GEN_0 :: PFRI_3_PAGE_BRK_INTR_INFO_1 :: BANK_ADDRESS [19:17] */
#define BCHP_MEMC_GEN_0_PFRI_3_PAGE_BRK_INTR_INFO_1_BANK_ADDRESS_MASK 0x000e0000
#define BCHP_MEMC_GEN_0_PFRI_3_PAGE_BRK_INTR_INFO_1_BANK_ADDRESS_SHIFT 17
#define BCHP_MEMC_GEN_0_PFRI_3_PAGE_BRK_INTR_INFO_1_BANK_ADDRESS_DEFAULT 0

/* MEMC_GEN_0 :: PFRI_3_PAGE_BRK_INTR_INFO_1 :: reserved1 [16:16] */
#define BCHP_MEMC_GEN_0_PFRI_3_PAGE_BRK_INTR_INFO_1_reserved1_MASK 0x00010000
#define BCHP_MEMC_GEN_0_PFRI_3_PAGE_BRK_INTR_INFO_1_reserved1_SHIFT 16

/* MEMC_GEN_0 :: PFRI_3_PAGE_BRK_INTR_INFO_1 :: ROW_ADDRESS [15:00] */
#define BCHP_MEMC_GEN_0_PFRI_3_PAGE_BRK_INTR_INFO_1_ROW_ADDRESS_MASK 0x0000ffff
#define BCHP_MEMC_GEN_0_PFRI_3_PAGE_BRK_INTR_INFO_1_ROW_ADDRESS_SHIFT 0
#define BCHP_MEMC_GEN_0_PFRI_3_PAGE_BRK_INTR_INFO_1_ROW_ADDRESS_DEFAULT 0

/***************************************************************************
 *PFRI_3_VIOLATION_INFO_WRITE_CLEAR - PFRI violation info write clear register for client 123
 ***************************************************************************/
/* MEMC_GEN_0 :: PFRI_3_VIOLATION_INFO_WRITE_CLEAR :: reserved0 [31:01] */
#define BCHP_MEMC_GEN_0_PFRI_3_VIOLATION_INFO_WRITE_CLEAR_reserved0_MASK 0xfffffffe
#define BCHP_MEMC_GEN_0_PFRI_3_VIOLATION_INFO_WRITE_CLEAR_reserved0_SHIFT 1

/* MEMC_GEN_0 :: PFRI_3_VIOLATION_INFO_WRITE_CLEAR :: WRITE_CLEAR [00:00] */
#define BCHP_MEMC_GEN_0_PFRI_3_VIOLATION_INFO_WRITE_CLEAR_WRITE_CLEAR_MASK 0x00000001
#define BCHP_MEMC_GEN_0_PFRI_3_VIOLATION_INFO_WRITE_CLEAR_WRITE_CLEAR_SHIFT 0
#define BCHP_MEMC_GEN_0_PFRI_3_VIOLATION_INFO_WRITE_CLEAR_WRITE_CLEAR_DEFAULT 0

/***************************************************************************
 *LMB_ADDRESS_ERROR_INFO - LMB un-aligned address error information register
 ***************************************************************************/
/* MEMC_GEN_0 :: LMB_ADDRESS_ERROR_INFO :: ADDR [31:00] */
#define BCHP_MEMC_GEN_0_LMB_ADDRESS_ERROR_INFO_ADDR_MASK           0xffffffff
#define BCHP_MEMC_GEN_0_LMB_ADDRESS_ERROR_INFO_ADDR_SHIFT          0
#define BCHP_MEMC_GEN_0_LMB_ADDRESS_ERROR_INFO_ADDR_DEFAULT        0

/***************************************************************************
 *LMB_ADDRESS_ERROR_INFO_WRITE_CLEAR - LMB un-aligned address error info write clear register
 ***************************************************************************/
/* MEMC_GEN_0 :: LMB_ADDRESS_ERROR_INFO_WRITE_CLEAR :: reserved0 [31:01] */
#define BCHP_MEMC_GEN_0_LMB_ADDRESS_ERROR_INFO_WRITE_CLEAR_reserved0_MASK 0xfffffffe
#define BCHP_MEMC_GEN_0_LMB_ADDRESS_ERROR_INFO_WRITE_CLEAR_reserved0_SHIFT 1

/* MEMC_GEN_0 :: LMB_ADDRESS_ERROR_INFO_WRITE_CLEAR :: WRITE_CLEAR [00:00] */
#define BCHP_MEMC_GEN_0_LMB_ADDRESS_ERROR_INFO_WRITE_CLEAR_WRITE_CLEAR_MASK 0x00000001
#define BCHP_MEMC_GEN_0_LMB_ADDRESS_ERROR_INFO_WRITE_CLEAR_WRITE_CLEAR_SHIFT 0
#define BCHP_MEMC_GEN_0_LMB_ADDRESS_ERROR_INFO_WRITE_CLEAR_WRITE_CLEAR_DEFAULT 0

/***************************************************************************
 *PFRI_0_LADDR_FIFO_DEPTH_COUNT - PFRI_0 Laddr fifo depth count register
 ***************************************************************************/
/* MEMC_GEN_0 :: PFRI_0_LADDR_FIFO_DEPTH_COUNT :: reserved0 [31:08] */
#define BCHP_MEMC_GEN_0_PFRI_0_LADDR_FIFO_DEPTH_COUNT_reserved0_MASK 0xffffff00
#define BCHP_MEMC_GEN_0_PFRI_0_LADDR_FIFO_DEPTH_COUNT_reserved0_SHIFT 8

/* MEMC_GEN_0 :: PFRI_0_LADDR_FIFO_DEPTH_COUNT :: DEPTH_COUNT [07:00] */
#define BCHP_MEMC_GEN_0_PFRI_0_LADDR_FIFO_DEPTH_COUNT_DEPTH_COUNT_MASK 0x000000ff
#define BCHP_MEMC_GEN_0_PFRI_0_LADDR_FIFO_DEPTH_COUNT_DEPTH_COUNT_SHIFT 0
#define BCHP_MEMC_GEN_0_PFRI_0_LADDR_FIFO_DEPTH_COUNT_DEPTH_COUNT_DEFAULT 72

/***************************************************************************
 *PFRI_1_LADDR_FIFO_DEPTH_COUNT - PFRI_1 Laddr fifo depth count register
 ***************************************************************************/
/* MEMC_GEN_0 :: PFRI_1_LADDR_FIFO_DEPTH_COUNT :: reserved0 [31:08] */
#define BCHP_MEMC_GEN_0_PFRI_1_LADDR_FIFO_DEPTH_COUNT_reserved0_MASK 0xffffff00
#define BCHP_MEMC_GEN_0_PFRI_1_LADDR_FIFO_DEPTH_COUNT_reserved0_SHIFT 8

/* MEMC_GEN_0 :: PFRI_1_LADDR_FIFO_DEPTH_COUNT :: DEPTH_COUNT [07:00] */
#define BCHP_MEMC_GEN_0_PFRI_1_LADDR_FIFO_DEPTH_COUNT_DEPTH_COUNT_MASK 0x000000ff
#define BCHP_MEMC_GEN_0_PFRI_1_LADDR_FIFO_DEPTH_COUNT_DEPTH_COUNT_SHIFT 0
#define BCHP_MEMC_GEN_0_PFRI_1_LADDR_FIFO_DEPTH_COUNT_DEPTH_COUNT_DEFAULT 72

/***************************************************************************
 *PFRI_2_LADDR_FIFO_DEPTH_COUNT - PFRI_2 Laddr fifo depth count register
 ***************************************************************************/
/* MEMC_GEN_0 :: PFRI_2_LADDR_FIFO_DEPTH_COUNT :: reserved0 [31:08] */
#define BCHP_MEMC_GEN_0_PFRI_2_LADDR_FIFO_DEPTH_COUNT_reserved0_MASK 0xffffff00
#define BCHP_MEMC_GEN_0_PFRI_2_LADDR_FIFO_DEPTH_COUNT_reserved0_SHIFT 8

/* MEMC_GEN_0 :: PFRI_2_LADDR_FIFO_DEPTH_COUNT :: DEPTH_COUNT [07:00] */
#define BCHP_MEMC_GEN_0_PFRI_2_LADDR_FIFO_DEPTH_COUNT_DEPTH_COUNT_MASK 0x000000ff
#define BCHP_MEMC_GEN_0_PFRI_2_LADDR_FIFO_DEPTH_COUNT_DEPTH_COUNT_SHIFT 0
#define BCHP_MEMC_GEN_0_PFRI_2_LADDR_FIFO_DEPTH_COUNT_DEPTH_COUNT_DEFAULT 72

/***************************************************************************
 *PFRI_3_LADDR_FIFO_DEPTH_COUNT - PFRI_3 Laddr fifo depth count register
 ***************************************************************************/
/* MEMC_GEN_0 :: PFRI_3_LADDR_FIFO_DEPTH_COUNT :: reserved0 [31:08] */
#define BCHP_MEMC_GEN_0_PFRI_3_LADDR_FIFO_DEPTH_COUNT_reserved0_MASK 0xffffff00
#define BCHP_MEMC_GEN_0_PFRI_3_LADDR_FIFO_DEPTH_COUNT_reserved0_SHIFT 8

/* MEMC_GEN_0 :: PFRI_3_LADDR_FIFO_DEPTH_COUNT :: DEPTH_COUNT [07:00] */
#define BCHP_MEMC_GEN_0_PFRI_3_LADDR_FIFO_DEPTH_COUNT_DEPTH_COUNT_MASK 0x000000ff
#define BCHP_MEMC_GEN_0_PFRI_3_LADDR_FIFO_DEPTH_COUNT_DEPTH_COUNT_SHIFT 0
#define BCHP_MEMC_GEN_0_PFRI_3_LADDR_FIFO_DEPTH_COUNT_DEPTH_COUNT_DEFAULT 72

/***************************************************************************
 *PFRI_0_TEST_CLIENT_COMMAND - PFRI_0 test client command register
 ***************************************************************************/
/* MEMC_GEN_0 :: PFRI_0_TEST_CLIENT_COMMAND :: COMMAND [31:00] */
#define BCHP_MEMC_GEN_0_PFRI_0_TEST_CLIENT_COMMAND_COMMAND_MASK    0xffffffff
#define BCHP_MEMC_GEN_0_PFRI_0_TEST_CLIENT_COMMAND_COMMAND_SHIFT   0
#define BCHP_MEMC_GEN_0_PFRI_0_TEST_CLIENT_COMMAND_COMMAND_DEFAULT 0

/***************************************************************************
 *PFRI_1_TEST_CLIENT_COMMAND - PFRI_1 test client command register
 ***************************************************************************/
/* MEMC_GEN_0 :: PFRI_1_TEST_CLIENT_COMMAND :: COMMAND [31:00] */
#define BCHP_MEMC_GEN_0_PFRI_1_TEST_CLIENT_COMMAND_COMMAND_MASK    0xffffffff
#define BCHP_MEMC_GEN_0_PFRI_1_TEST_CLIENT_COMMAND_COMMAND_SHIFT   0
#define BCHP_MEMC_GEN_0_PFRI_1_TEST_CLIENT_COMMAND_COMMAND_DEFAULT 0

/***************************************************************************
 *PFRI_2_TEST_CLIENT_COMMAND - PFRI_2 test client command register
 ***************************************************************************/
/* MEMC_GEN_0 :: PFRI_2_TEST_CLIENT_COMMAND :: COMMAND [31:00] */
#define BCHP_MEMC_GEN_0_PFRI_2_TEST_CLIENT_COMMAND_COMMAND_MASK    0xffffffff
#define BCHP_MEMC_GEN_0_PFRI_2_TEST_CLIENT_COMMAND_COMMAND_SHIFT   0
#define BCHP_MEMC_GEN_0_PFRI_2_TEST_CLIENT_COMMAND_COMMAND_DEFAULT 0

/***************************************************************************
 *PFRI_3_TEST_CLIENT_COMMAND - PFRI_3 test client command register
 ***************************************************************************/
/* MEMC_GEN_0 :: PFRI_3_TEST_CLIENT_COMMAND :: COMMAND [31:00] */
#define BCHP_MEMC_GEN_0_PFRI_3_TEST_CLIENT_COMMAND_COMMAND_MASK    0xffffffff
#define BCHP_MEMC_GEN_0_PFRI_3_TEST_CLIENT_COMMAND_COMMAND_SHIFT   0
#define BCHP_MEMC_GEN_0_PFRI_3_TEST_CLIENT_COMMAND_COMMAND_DEFAULT 0

/***************************************************************************
 *PFRI_0_TEST_CLIENT_BUSY_FLAG - PFRI_0 test client busy flag register
 ***************************************************************************/
/* MEMC_GEN_0 :: PFRI_0_TEST_CLIENT_BUSY_FLAG :: reserved0 [31:01] */
#define BCHP_MEMC_GEN_0_PFRI_0_TEST_CLIENT_BUSY_FLAG_reserved0_MASK 0xfffffffe
#define BCHP_MEMC_GEN_0_PFRI_0_TEST_CLIENT_BUSY_FLAG_reserved0_SHIFT 1

/* MEMC_GEN_0 :: PFRI_0_TEST_CLIENT_BUSY_FLAG :: BUSY_FLAG [00:00] */
#define BCHP_MEMC_GEN_0_PFRI_0_TEST_CLIENT_BUSY_FLAG_BUSY_FLAG_MASK 0x00000001
#define BCHP_MEMC_GEN_0_PFRI_0_TEST_CLIENT_BUSY_FLAG_BUSY_FLAG_SHIFT 0
#define BCHP_MEMC_GEN_0_PFRI_0_TEST_CLIENT_BUSY_FLAG_BUSY_FLAG_DEFAULT 0

/***************************************************************************
 *PFRI_1_TEST_CLIENT_BUSY_FLAG - PFRI_1 test client busy flag register
 ***************************************************************************/
/* MEMC_GEN_0 :: PFRI_1_TEST_CLIENT_BUSY_FLAG :: reserved0 [31:01] */
#define BCHP_MEMC_GEN_0_PFRI_1_TEST_CLIENT_BUSY_FLAG_reserved0_MASK 0xfffffffe
#define BCHP_MEMC_GEN_0_PFRI_1_TEST_CLIENT_BUSY_FLAG_reserved0_SHIFT 1

/* MEMC_GEN_0 :: PFRI_1_TEST_CLIENT_BUSY_FLAG :: BUSY_FLAG [00:00] */
#define BCHP_MEMC_GEN_0_PFRI_1_TEST_CLIENT_BUSY_FLAG_BUSY_FLAG_MASK 0x00000001
#define BCHP_MEMC_GEN_0_PFRI_1_TEST_CLIENT_BUSY_FLAG_BUSY_FLAG_SHIFT 0
#define BCHP_MEMC_GEN_0_PFRI_1_TEST_CLIENT_BUSY_FLAG_BUSY_FLAG_DEFAULT 0

/***************************************************************************
 *PFRI_2_TEST_CLIENT_BUSY_FLAG - PFRI_2 test client busy flag register
 ***************************************************************************/
/* MEMC_GEN_0 :: PFRI_2_TEST_CLIENT_BUSY_FLAG :: reserved0 [31:01] */
#define BCHP_MEMC_GEN_0_PFRI_2_TEST_CLIENT_BUSY_FLAG_reserved0_MASK 0xfffffffe
#define BCHP_MEMC_GEN_0_PFRI_2_TEST_CLIENT_BUSY_FLAG_reserved0_SHIFT 1

/* MEMC_GEN_0 :: PFRI_2_TEST_CLIENT_BUSY_FLAG :: BUSY_FLAG [00:00] */
#define BCHP_MEMC_GEN_0_PFRI_2_TEST_CLIENT_BUSY_FLAG_BUSY_FLAG_MASK 0x00000001
#define BCHP_MEMC_GEN_0_PFRI_2_TEST_CLIENT_BUSY_FLAG_BUSY_FLAG_SHIFT 0
#define BCHP_MEMC_GEN_0_PFRI_2_TEST_CLIENT_BUSY_FLAG_BUSY_FLAG_DEFAULT 0

/***************************************************************************
 *PFRI_3_TEST_CLIENT_BUSY_FLAG - PFRI_3 test client busy flag register
 ***************************************************************************/
/* MEMC_GEN_0 :: PFRI_3_TEST_CLIENT_BUSY_FLAG :: reserved0 [31:01] */
#define BCHP_MEMC_GEN_0_PFRI_3_TEST_CLIENT_BUSY_FLAG_reserved0_MASK 0xfffffffe
#define BCHP_MEMC_GEN_0_PFRI_3_TEST_CLIENT_BUSY_FLAG_reserved0_SHIFT 1

/* MEMC_GEN_0 :: PFRI_3_TEST_CLIENT_BUSY_FLAG :: BUSY_FLAG [00:00] */
#define BCHP_MEMC_GEN_0_PFRI_3_TEST_CLIENT_BUSY_FLAG_BUSY_FLAG_MASK 0x00000001
#define BCHP_MEMC_GEN_0_PFRI_3_TEST_CLIENT_BUSY_FLAG_BUSY_FLAG_SHIFT 0
#define BCHP_MEMC_GEN_0_PFRI_3_TEST_CLIENT_BUSY_FLAG_BUSY_FLAG_DEFAULT 0

/***************************************************************************
 *SPARE_1 - Spare Register 1 .
 ***************************************************************************/
/* MEMC_GEN_0 :: SPARE_1 :: SPARE [31:00] */
#define BCHP_MEMC_GEN_0_SPARE_1_SPARE_MASK                         0xffffffff
#define BCHP_MEMC_GEN_0_SPARE_1_SPARE_SHIFT                        0
#define BCHP_MEMC_GEN_0_SPARE_1_SPARE_DEFAULT                      0

/***************************************************************************
 *SPARE_2 - Spare Register 2 .
 ***************************************************************************/
/* MEMC_GEN_0 :: SPARE_2 :: SPARE [31:00] */
#define BCHP_MEMC_GEN_0_SPARE_2_SPARE_MASK                         0xffffffff
#define BCHP_MEMC_GEN_0_SPARE_2_SPARE_SHIFT                        0
#define BCHP_MEMC_GEN_0_SPARE_2_SPARE_DEFAULT                      0

/***************************************************************************
 *SPARE_RO_1 - Read only Spare Register 0 .
 ***************************************************************************/
/* MEMC_GEN_0 :: SPARE_RO_1 :: SPARE_RO [31:00] */
#define BCHP_MEMC_GEN_0_SPARE_RO_1_SPARE_RO_MASK                   0xffffffff
#define BCHP_MEMC_GEN_0_SPARE_RO_1_SPARE_RO_SHIFT                  0
#define BCHP_MEMC_GEN_0_SPARE_RO_1_SPARE_RO_DEFAULT                0

/***************************************************************************
 *SPARE_RO_2 - Read only Spare Register 1 .
 ***************************************************************************/
/* MEMC_GEN_0 :: SPARE_RO_2 :: SPARE_RO [31:00] */
#define BCHP_MEMC_GEN_0_SPARE_RO_2_SPARE_RO_MASK                   0xffffffff
#define BCHP_MEMC_GEN_0_SPARE_RO_2_SPARE_RO_SHIFT                  0
#define BCHP_MEMC_GEN_0_SPARE_RO_2_SPARE_RO_DEFAULT                0

/***************************************************************************
 *TP_CORE_SEL - Test port selection register.
 ***************************************************************************/
/* MEMC_GEN_0 :: TP_CORE_SEL :: reserved0 [31:05] */
#define BCHP_MEMC_GEN_0_TP_CORE_SEL_reserved0_MASK                 0xffffffe0
#define BCHP_MEMC_GEN_0_TP_CORE_SEL_reserved0_SHIFT                5

/* MEMC_GEN_0 :: TP_CORE_SEL :: TP_CORE_SEL [04:00] */
#define BCHP_MEMC_GEN_0_TP_CORE_SEL_TP_CORE_SEL_MASK               0x0000001f
#define BCHP_MEMC_GEN_0_TP_CORE_SEL_TP_CORE_SEL_SHIFT              0
#define BCHP_MEMC_GEN_0_TP_CORE_SEL_TP_CORE_SEL_DEFAULT            0

/***************************************************************************
 *PFRI_4_PAGE_BRK_INTR_INFO_0 - PFRI Page Break Interrupt Information Register 0 for client 116
 ***************************************************************************/
/* MEMC_GEN_0 :: PFRI_4_PAGE_BRK_INTR_INFO_0 :: reserved0 [31:20] */
#define BCHP_MEMC_GEN_0_PFRI_4_PAGE_BRK_INTR_INFO_0_reserved0_MASK 0xfff00000
#define BCHP_MEMC_GEN_0_PFRI_4_PAGE_BRK_INTR_INFO_0_reserved0_SHIFT 20

/* MEMC_GEN_0 :: PFRI_4_PAGE_BRK_INTR_INFO_0 :: BANK_ADDRESS [19:17] */
#define BCHP_MEMC_GEN_0_PFRI_4_PAGE_BRK_INTR_INFO_0_BANK_ADDRESS_MASK 0x000e0000
#define BCHP_MEMC_GEN_0_PFRI_4_PAGE_BRK_INTR_INFO_0_BANK_ADDRESS_SHIFT 17
#define BCHP_MEMC_GEN_0_PFRI_4_PAGE_BRK_INTR_INFO_0_BANK_ADDRESS_DEFAULT 0

/* MEMC_GEN_0 :: PFRI_4_PAGE_BRK_INTR_INFO_0 :: reserved1 [16:16] */
#define BCHP_MEMC_GEN_0_PFRI_4_PAGE_BRK_INTR_INFO_0_reserved1_MASK 0x00010000
#define BCHP_MEMC_GEN_0_PFRI_4_PAGE_BRK_INTR_INFO_0_reserved1_SHIFT 16

/* MEMC_GEN_0 :: PFRI_4_PAGE_BRK_INTR_INFO_0 :: ROW_ADDRESS [15:00] */
#define BCHP_MEMC_GEN_0_PFRI_4_PAGE_BRK_INTR_INFO_0_ROW_ADDRESS_MASK 0x0000ffff
#define BCHP_MEMC_GEN_0_PFRI_4_PAGE_BRK_INTR_INFO_0_ROW_ADDRESS_SHIFT 0
#define BCHP_MEMC_GEN_0_PFRI_4_PAGE_BRK_INTR_INFO_0_ROW_ADDRESS_DEFAULT 0

/***************************************************************************
 *PFRI_4_PAGE_BRK_INTR_INFO_1 - PFRI Page Break Interrupt Information Register 1 for client 116
 ***************************************************************************/
/* MEMC_GEN_0 :: PFRI_4_PAGE_BRK_INTR_INFO_1 :: reserved0 [31:20] */
#define BCHP_MEMC_GEN_0_PFRI_4_PAGE_BRK_INTR_INFO_1_reserved0_MASK 0xfff00000
#define BCHP_MEMC_GEN_0_PFRI_4_PAGE_BRK_INTR_INFO_1_reserved0_SHIFT 20

/* MEMC_GEN_0 :: PFRI_4_PAGE_BRK_INTR_INFO_1 :: BANK_ADDRESS [19:17] */
#define BCHP_MEMC_GEN_0_PFRI_4_PAGE_BRK_INTR_INFO_1_BANK_ADDRESS_MASK 0x000e0000
#define BCHP_MEMC_GEN_0_PFRI_4_PAGE_BRK_INTR_INFO_1_BANK_ADDRESS_SHIFT 17
#define BCHP_MEMC_GEN_0_PFRI_4_PAGE_BRK_INTR_INFO_1_BANK_ADDRESS_DEFAULT 0

/* MEMC_GEN_0 :: PFRI_4_PAGE_BRK_INTR_INFO_1 :: reserved1 [16:16] */
#define BCHP_MEMC_GEN_0_PFRI_4_PAGE_BRK_INTR_INFO_1_reserved1_MASK 0x00010000
#define BCHP_MEMC_GEN_0_PFRI_4_PAGE_BRK_INTR_INFO_1_reserved1_SHIFT 16

/* MEMC_GEN_0 :: PFRI_4_PAGE_BRK_INTR_INFO_1 :: ROW_ADDRESS [15:00] */
#define BCHP_MEMC_GEN_0_PFRI_4_PAGE_BRK_INTR_INFO_1_ROW_ADDRESS_MASK 0x0000ffff
#define BCHP_MEMC_GEN_0_PFRI_4_PAGE_BRK_INTR_INFO_1_ROW_ADDRESS_SHIFT 0
#define BCHP_MEMC_GEN_0_PFRI_4_PAGE_BRK_INTR_INFO_1_ROW_ADDRESS_DEFAULT 0

/***************************************************************************
 *PFRI_4_VIOLATION_INFO_WRITE_CLEAR - PFRI violation info write clear register for client 116
 ***************************************************************************/
/* MEMC_GEN_0 :: PFRI_4_VIOLATION_INFO_WRITE_CLEAR :: reserved0 [31:01] */
#define BCHP_MEMC_GEN_0_PFRI_4_VIOLATION_INFO_WRITE_CLEAR_reserved0_MASK 0xfffffffe
#define BCHP_MEMC_GEN_0_PFRI_4_VIOLATION_INFO_WRITE_CLEAR_reserved0_SHIFT 1

/* MEMC_GEN_0 :: PFRI_4_VIOLATION_INFO_WRITE_CLEAR :: WRITE_CLEAR [00:00] */
#define BCHP_MEMC_GEN_0_PFRI_4_VIOLATION_INFO_WRITE_CLEAR_WRITE_CLEAR_MASK 0x00000001
#define BCHP_MEMC_GEN_0_PFRI_4_VIOLATION_INFO_WRITE_CLEAR_WRITE_CLEAR_SHIFT 0
#define BCHP_MEMC_GEN_0_PFRI_4_VIOLATION_INFO_WRITE_CLEAR_WRITE_CLEAR_DEFAULT 0

/***************************************************************************
 *PFRI_4_LADDR_FIFO_DEPTH_COUNT - PFRI_4 Laddr fifo depth count register
 ***************************************************************************/
/* MEMC_GEN_0 :: PFRI_4_LADDR_FIFO_DEPTH_COUNT :: reserved0 [31:08] */
#define BCHP_MEMC_GEN_0_PFRI_4_LADDR_FIFO_DEPTH_COUNT_reserved0_MASK 0xffffff00
#define BCHP_MEMC_GEN_0_PFRI_4_LADDR_FIFO_DEPTH_COUNT_reserved0_SHIFT 8

/* MEMC_GEN_0 :: PFRI_4_LADDR_FIFO_DEPTH_COUNT :: DEPTH_COUNT [07:00] */
#define BCHP_MEMC_GEN_0_PFRI_4_LADDR_FIFO_DEPTH_COUNT_DEPTH_COUNT_MASK 0x000000ff
#define BCHP_MEMC_GEN_0_PFRI_4_LADDR_FIFO_DEPTH_COUNT_DEPTH_COUNT_SHIFT 0
#define BCHP_MEMC_GEN_0_PFRI_4_LADDR_FIFO_DEPTH_COUNT_DEPTH_COUNT_DEFAULT 72

/***************************************************************************
 *PFRI_4_TEST_CLIENT_COMMAND - PFRI_4 test client command register
 ***************************************************************************/
/* MEMC_GEN_0 :: PFRI_4_TEST_CLIENT_COMMAND :: COMMAND [31:00] */
#define BCHP_MEMC_GEN_0_PFRI_4_TEST_CLIENT_COMMAND_COMMAND_MASK    0xffffffff
#define BCHP_MEMC_GEN_0_PFRI_4_TEST_CLIENT_COMMAND_COMMAND_SHIFT   0
#define BCHP_MEMC_GEN_0_PFRI_4_TEST_CLIENT_COMMAND_COMMAND_DEFAULT 0

/***************************************************************************
 *PFRI_4_TEST_CLIENT_BUSY_FLAG - PFRI_4 test client busy flag register
 ***************************************************************************/
/* MEMC_GEN_0 :: PFRI_4_TEST_CLIENT_BUSY_FLAG :: reserved0 [31:01] */
#define BCHP_MEMC_GEN_0_PFRI_4_TEST_CLIENT_BUSY_FLAG_reserved0_MASK 0xfffffffe
#define BCHP_MEMC_GEN_0_PFRI_4_TEST_CLIENT_BUSY_FLAG_reserved0_SHIFT 1

/* MEMC_GEN_0 :: PFRI_4_TEST_CLIENT_BUSY_FLAG :: BUSY_FLAG [00:00] */
#define BCHP_MEMC_GEN_0_PFRI_4_TEST_CLIENT_BUSY_FLAG_BUSY_FLAG_MASK 0x00000001
#define BCHP_MEMC_GEN_0_PFRI_4_TEST_CLIENT_BUSY_FLAG_BUSY_FLAG_SHIFT 0
#define BCHP_MEMC_GEN_0_PFRI_4_TEST_CLIENT_BUSY_FLAG_BUSY_FLAG_DEFAULT 0

/***************************************************************************
 *MISC_BIU_MSA_REG - PFRI_4 test client busy flag register
 ***************************************************************************/
/* MEMC_GEN_0 :: MISC_BIU_MSA_REG :: reserved0 [31:07] */
#define BCHP_MEMC_GEN_0_MISC_BIU_MSA_REG_reserved0_MASK            0xffffff80
#define BCHP_MEMC_GEN_0_MISC_BIU_MSA_REG_reserved0_SHIFT           7

/* MEMC_GEN_0 :: MISC_BIU_MSA_REG :: ARB_FULLNESS_UPDATE_ECO_DISABLE [06:05] */
#define BCHP_MEMC_GEN_0_MISC_BIU_MSA_REG_ARB_FULLNESS_UPDATE_ECO_DISABLE_MASK 0x00000060
#define BCHP_MEMC_GEN_0_MISC_BIU_MSA_REG_ARB_FULLNESS_UPDATE_ECO_DISABLE_SHIFT 5
#define BCHP_MEMC_GEN_0_MISC_BIU_MSA_REG_ARB_FULLNESS_UPDATE_ECO_DISABLE_DEFAULT 0

/* MEMC_GEN_0 :: MISC_BIU_MSA_REG :: LMB_ARB_FIX [04:04] */
#define BCHP_MEMC_GEN_0_MISC_BIU_MSA_REG_LMB_ARB_FIX_MASK          0x00000010
#define BCHP_MEMC_GEN_0_MISC_BIU_MSA_REG_LMB_ARB_FIX_SHIFT         4
#define BCHP_MEMC_GEN_0_MISC_BIU_MSA_REG_LMB_ARB_FIX_DEFAULT       1

/* MEMC_GEN_0 :: MISC_BIU_MSA_REG :: RASTER_WRITE_FIX [03:03] */
#define BCHP_MEMC_GEN_0_MISC_BIU_MSA_REG_RASTER_WRITE_FIX_MASK     0x00000008
#define BCHP_MEMC_GEN_0_MISC_BIU_MSA_REG_RASTER_WRITE_FIX_SHIFT    3
#define BCHP_MEMC_GEN_0_MISC_BIU_MSA_REG_RASTER_WRITE_FIX_DEFAULT  1

/* MEMC_GEN_0 :: MISC_BIU_MSA_REG :: LMB_FIFO_ACCEPT_4 [02:02] */
#define BCHP_MEMC_GEN_0_MISC_BIU_MSA_REG_LMB_FIFO_ACCEPT_4_MASK    0x00000004
#define BCHP_MEMC_GEN_0_MISC_BIU_MSA_REG_LMB_FIFO_ACCEPT_4_SHIFT   2
#define BCHP_MEMC_GEN_0_MISC_BIU_MSA_REG_LMB_FIFO_ACCEPT_4_DEFAULT 0

/* MEMC_GEN_0 :: MISC_BIU_MSA_REG :: LFSR_4_ABORT_SEL [01:01] */
#define BCHP_MEMC_GEN_0_MISC_BIU_MSA_REG_LFSR_4_ABORT_SEL_MASK     0x00000002
#define BCHP_MEMC_GEN_0_MISC_BIU_MSA_REG_LFSR_4_ABORT_SEL_SHIFT    1
#define BCHP_MEMC_GEN_0_MISC_BIU_MSA_REG_LFSR_4_ABORT_SEL_DEFAULT  0

/* MEMC_GEN_0 :: MISC_BIU_MSA_REG :: DISABLE_MSA_SCB_OR_TREE [00:00] */
#define BCHP_MEMC_GEN_0_MISC_BIU_MSA_REG_DISABLE_MSA_SCB_OR_TREE_MASK 0x00000001
#define BCHP_MEMC_GEN_0_MISC_BIU_MSA_REG_DISABLE_MSA_SCB_OR_TREE_SHIFT 0
#define BCHP_MEMC_GEN_0_MISC_BIU_MSA_REG_DISABLE_MSA_SCB_OR_TREE_DEFAULT 0

/***************************************************************************
 *DIS_CLIENT1_CMD - DDR interface stress client 1 command register.
 ***************************************************************************/
/* MEMC_GEN_0 :: DIS_CLIENT1_CMD :: reserved0 [31:26] */
#define BCHP_MEMC_GEN_0_DIS_CLIENT1_CMD_reserved0_MASK             0xfc000000
#define BCHP_MEMC_GEN_0_DIS_CLIENT1_CMD_reserved0_SHIFT            26

/* MEMC_GEN_0 :: DIS_CLIENT1_CMD :: BYPASS_PADS [25:25] */
#define BCHP_MEMC_GEN_0_DIS_CLIENT1_CMD_BYPASS_PADS_MASK           0x02000000
#define BCHP_MEMC_GEN_0_DIS_CLIENT1_CMD_BYPASS_PADS_SHIFT          25
#define BCHP_MEMC_GEN_0_DIS_CLIENT1_CMD_BYPASS_PADS_DEFAULT        1
#define BCHP_MEMC_GEN_0_DIS_CLIENT1_CMD_BYPASS_PADS_YES            1
#define BCHP_MEMC_GEN_0_DIS_CLIENT1_CMD_BYPASS_PADS_NO             0

/* MEMC_GEN_0 :: DIS_CLIENT1_CMD :: MODE [24:23] */
#define BCHP_MEMC_GEN_0_DIS_CLIENT1_CMD_MODE_MASK                  0x01800000
#define BCHP_MEMC_GEN_0_DIS_CLIENT1_CMD_MODE_SHIFT                 23
#define BCHP_MEMC_GEN_0_DIS_CLIENT1_CMD_MODE_DEFAULT               0

/* MEMC_GEN_0 :: DIS_CLIENT1_CMD :: DATA_PATTERN [22:21] */
#define BCHP_MEMC_GEN_0_DIS_CLIENT1_CMD_DATA_PATTERN_MASK          0x00600000
#define BCHP_MEMC_GEN_0_DIS_CLIENT1_CMD_DATA_PATTERN_SHIFT         21
#define BCHP_MEMC_GEN_0_DIS_CLIENT1_CMD_DATA_PATTERN_DEFAULT       0

/* MEMC_GEN_0 :: DIS_CLIENT1_CMD :: BURST_LEN [20:16] */
#define BCHP_MEMC_GEN_0_DIS_CLIENT1_CMD_BURST_LEN_MASK             0x001f0000
#define BCHP_MEMC_GEN_0_DIS_CLIENT1_CMD_BURST_LEN_SHIFT            16
#define BCHP_MEMC_GEN_0_DIS_CLIENT1_CMD_BURST_LEN_DEFAULT          0

/* MEMC_GEN_0 :: DIS_CLIENT1_CMD :: STEP_SIZE [15:00] */
#define BCHP_MEMC_GEN_0_DIS_CLIENT1_CMD_STEP_SIZE_MASK             0x0000ffff
#define BCHP_MEMC_GEN_0_DIS_CLIENT1_CMD_STEP_SIZE_SHIFT            0
#define BCHP_MEMC_GEN_0_DIS_CLIENT1_CMD_STEP_SIZE_DEFAULT          0

/***************************************************************************
 *DIS_CLIENT1_START_ADDR - DDR interface stress client 1 start address register.
 ***************************************************************************/
/* MEMC_GEN_0 :: DIS_CLIENT1_START_ADDR :: reserved0 [31:29] */
#define BCHP_MEMC_GEN_0_DIS_CLIENT1_START_ADDR_reserved0_MASK      0xe0000000
#define BCHP_MEMC_GEN_0_DIS_CLIENT1_START_ADDR_reserved0_SHIFT     29

/* MEMC_GEN_0 :: DIS_CLIENT1_START_ADDR :: START_ADDR [28:00] */
#define BCHP_MEMC_GEN_0_DIS_CLIENT1_START_ADDR_START_ADDR_MASK     0x1fffffff
#define BCHP_MEMC_GEN_0_DIS_CLIENT1_START_ADDR_START_ADDR_SHIFT    0
#define BCHP_MEMC_GEN_0_DIS_CLIENT1_START_ADDR_START_ADDR_DEFAULT  0

/***************************************************************************
 *DIS_CLIENT1_END_ADDR - DDR interface stress client 1 end address register.
 ***************************************************************************/
/* MEMC_GEN_0 :: DIS_CLIENT1_END_ADDR :: reserved0 [31:31] */
#define BCHP_MEMC_GEN_0_DIS_CLIENT1_END_ADDR_reserved0_MASK        0x80000000
#define BCHP_MEMC_GEN_0_DIS_CLIENT1_END_ADDR_reserved0_SHIFT       31

/* MEMC_GEN_0 :: DIS_CLIENT1_END_ADDR :: LOOP_MODE [30:30] */
#define BCHP_MEMC_GEN_0_DIS_CLIENT1_END_ADDR_LOOP_MODE_MASK        0x40000000
#define BCHP_MEMC_GEN_0_DIS_CLIENT1_END_ADDR_LOOP_MODE_SHIFT       30
#define BCHP_MEMC_GEN_0_DIS_CLIENT1_END_ADDR_LOOP_MODE_DEFAULT     0

/* MEMC_GEN_0 :: DIS_CLIENT1_END_ADDR :: DISABLE_TIMEOUT [29:29] */
#define BCHP_MEMC_GEN_0_DIS_CLIENT1_END_ADDR_DISABLE_TIMEOUT_MASK  0x20000000
#define BCHP_MEMC_GEN_0_DIS_CLIENT1_END_ADDR_DISABLE_TIMEOUT_SHIFT 29
#define BCHP_MEMC_GEN_0_DIS_CLIENT1_END_ADDR_DISABLE_TIMEOUT_DEFAULT 0

/* MEMC_GEN_0 :: DIS_CLIENT1_END_ADDR :: END_ADDR [28:00] */
#define BCHP_MEMC_GEN_0_DIS_CLIENT1_END_ADDR_END_ADDR_MASK         0x1fffffff
#define BCHP_MEMC_GEN_0_DIS_CLIENT1_END_ADDR_END_ADDR_SHIFT        0
#define BCHP_MEMC_GEN_0_DIS_CLIENT1_END_ADDR_END_ADDR_DEFAULT      0

/***************************************************************************
 *DIS_CLIENT1_DQM - DDR interface stress client 1 DQM Register
 ***************************************************************************/
/* MEMC_GEN_0 :: DIS_CLIENT1_DQM :: DQM [31:00] */
#define BCHP_MEMC_GEN_0_DIS_CLIENT1_DQM_DQM_MASK                   0xffffffff
#define BCHP_MEMC_GEN_0_DIS_CLIENT1_DQM_DQM_SHIFT                  0
#define BCHP_MEMC_GEN_0_DIS_CLIENT1_DQM_DQM_DEFAULT                0

/***************************************************************************
 *DIS_CLIENT1_TRIGGER - DDR interface stress client 1 start register.
 ***************************************************************************/
/* MEMC_GEN_0 :: DIS_CLIENT1_TRIGGER :: reserved0 [31:01] */
#define BCHP_MEMC_GEN_0_DIS_CLIENT1_TRIGGER_reserved0_MASK         0xfffffffe
#define BCHP_MEMC_GEN_0_DIS_CLIENT1_TRIGGER_reserved0_SHIFT        1

/* MEMC_GEN_0 :: DIS_CLIENT1_TRIGGER :: START_TEST [00:00] */
#define BCHP_MEMC_GEN_0_DIS_CLIENT1_TRIGGER_START_TEST_MASK        0x00000001
#define BCHP_MEMC_GEN_0_DIS_CLIENT1_TRIGGER_START_TEST_SHIFT       0
#define BCHP_MEMC_GEN_0_DIS_CLIENT1_TRIGGER_START_TEST_DEFAULT     0

/***************************************************************************
 *DIS_CLIENT1_STATUS - DDR interface stress client 1 status register.
 ***************************************************************************/
/* MEMC_GEN_0 :: DIS_CLIENT1_STATUS :: reserved0 [31:11] */
#define BCHP_MEMC_GEN_0_DIS_CLIENT1_STATUS_reserved0_MASK          0xfffff800
#define BCHP_MEMC_GEN_0_DIS_CLIENT1_STATUS_reserved0_SHIFT         11

/* MEMC_GEN_0 :: DIS_CLIENT1_STATUS :: TIMEOUT_OCCURED [10:10] */
#define BCHP_MEMC_GEN_0_DIS_CLIENT1_STATUS_TIMEOUT_OCCURED_MASK    0x00000400
#define BCHP_MEMC_GEN_0_DIS_CLIENT1_STATUS_TIMEOUT_OCCURED_SHIFT   10
#define BCHP_MEMC_GEN_0_DIS_CLIENT1_STATUS_TIMEOUT_OCCURED_DEFAULT 0

/* MEMC_GEN_0 :: DIS_CLIENT1_STATUS :: CURRENT_STATE [09:08] */
#define BCHP_MEMC_GEN_0_DIS_CLIENT1_STATUS_CURRENT_STATE_MASK      0x00000300
#define BCHP_MEMC_GEN_0_DIS_CLIENT1_STATUS_CURRENT_STATE_SHIFT     8
#define BCHP_MEMC_GEN_0_DIS_CLIENT1_STATUS_CURRENT_STATE_DEFAULT   0

/* MEMC_GEN_0 :: DIS_CLIENT1_STATUS :: DQM_MATCH [07:04] */
#define BCHP_MEMC_GEN_0_DIS_CLIENT1_STATUS_DQM_MATCH_MASK          0x000000f0
#define BCHP_MEMC_GEN_0_DIS_CLIENT1_STATUS_DQM_MATCH_SHIFT         4
#define BCHP_MEMC_GEN_0_DIS_CLIENT1_STATUS_DQM_MATCH_DEFAULT       0

/* MEMC_GEN_0 :: DIS_CLIENT1_STATUS :: ADDR_CTRL_MATCH_SET1 [03:03] */
#define BCHP_MEMC_GEN_0_DIS_CLIENT1_STATUS_ADDR_CTRL_MATCH_SET1_MASK 0x00000008
#define BCHP_MEMC_GEN_0_DIS_CLIENT1_STATUS_ADDR_CTRL_MATCH_SET1_SHIFT 3
#define BCHP_MEMC_GEN_0_DIS_CLIENT1_STATUS_ADDR_CTRL_MATCH_SET1_DEFAULT 0
#define BCHP_MEMC_GEN_0_DIS_CLIENT1_STATUS_ADDR_CTRL_MATCH_SET1_YES 1
#define BCHP_MEMC_GEN_0_DIS_CLIENT1_STATUS_ADDR_CTRL_MATCH_SET1_NO 0

/* MEMC_GEN_0 :: DIS_CLIENT1_STATUS :: ADDR_CTRL_MATCH_SET0 [02:02] */
#define BCHP_MEMC_GEN_0_DIS_CLIENT1_STATUS_ADDR_CTRL_MATCH_SET0_MASK 0x00000004
#define BCHP_MEMC_GEN_0_DIS_CLIENT1_STATUS_ADDR_CTRL_MATCH_SET0_SHIFT 2
#define BCHP_MEMC_GEN_0_DIS_CLIENT1_STATUS_ADDR_CTRL_MATCH_SET0_DEFAULT 0
#define BCHP_MEMC_GEN_0_DIS_CLIENT1_STATUS_ADDR_CTRL_MATCH_SET0_YES 1
#define BCHP_MEMC_GEN_0_DIS_CLIENT1_STATUS_ADDR_CTRL_MATCH_SET0_NO 0

/* MEMC_GEN_0 :: DIS_CLIENT1_STATUS :: LBIST_TEST_PASSED [01:01] */
#define BCHP_MEMC_GEN_0_DIS_CLIENT1_STATUS_LBIST_TEST_PASSED_MASK  0x00000002
#define BCHP_MEMC_GEN_0_DIS_CLIENT1_STATUS_LBIST_TEST_PASSED_SHIFT 1
#define BCHP_MEMC_GEN_0_DIS_CLIENT1_STATUS_LBIST_TEST_PASSED_DEFAULT 0
#define BCHP_MEMC_GEN_0_DIS_CLIENT1_STATUS_LBIST_TEST_PASSED_YES   1
#define BCHP_MEMC_GEN_0_DIS_CLIENT1_STATUS_LBIST_TEST_PASSED_NO    0

/* MEMC_GEN_0 :: DIS_CLIENT1_STATUS :: TEST_DONE [00:00] */
#define BCHP_MEMC_GEN_0_DIS_CLIENT1_STATUS_TEST_DONE_MASK          0x00000001
#define BCHP_MEMC_GEN_0_DIS_CLIENT1_STATUS_TEST_DONE_SHIFT         0
#define BCHP_MEMC_GEN_0_DIS_CLIENT1_STATUS_TEST_DONE_DEFAULT       0
#define BCHP_MEMC_GEN_0_DIS_CLIENT1_STATUS_TEST_DONE_YES           1
#define BCHP_MEMC_GEN_0_DIS_CLIENT1_STATUS_TEST_DONE_NO            0

/***************************************************************************
 *DIS_CLIENT1_STATUS_1 - DDR interface stress client 1 status register.
 ***************************************************************************/
/* MEMC_GEN_0 :: DIS_CLIENT1_STATUS_1 :: DATA_CRC_MATCH [31:00] */
#define BCHP_MEMC_GEN_0_DIS_CLIENT1_STATUS_1_DATA_CRC_MATCH_MASK   0xffffffff
#define BCHP_MEMC_GEN_0_DIS_CLIENT1_STATUS_1_DATA_CRC_MATCH_SHIFT  0
#define BCHP_MEMC_GEN_0_DIS_CLIENT1_STATUS_1_DATA_CRC_MATCH_DEFAULT 0

/***************************************************************************
 *DIS_CLIENT1_STATUS_2 - DDR interface stress client 1 status register.
 ***************************************************************************/
/* MEMC_GEN_0 :: DIS_CLIENT1_STATUS_2 :: WRITE_JWORD_COUNT [31:00] */
#define BCHP_MEMC_GEN_0_DIS_CLIENT1_STATUS_2_WRITE_JWORD_COUNT_MASK 0xffffffff
#define BCHP_MEMC_GEN_0_DIS_CLIENT1_STATUS_2_WRITE_JWORD_COUNT_SHIFT 0
#define BCHP_MEMC_GEN_0_DIS_CLIENT1_STATUS_2_WRITE_JWORD_COUNT_DEFAULT 0

/***************************************************************************
 *DIS_CLIENT1_STATUS_3 - DDR interface stress client 1 status register.
 ***************************************************************************/
/* MEMC_GEN_0 :: DIS_CLIENT1_STATUS_3 :: READ_JWORD_COUNT [31:00] */
#define BCHP_MEMC_GEN_0_DIS_CLIENT1_STATUS_3_READ_JWORD_COUNT_MASK 0xffffffff
#define BCHP_MEMC_GEN_0_DIS_CLIENT1_STATUS_3_READ_JWORD_COUNT_SHIFT 0
#define BCHP_MEMC_GEN_0_DIS_CLIENT1_STATUS_3_READ_JWORD_COUNT_DEFAULT 0

#endif /* #ifndef BCHP_MEMC_GEN_0_H__ */

/* End of File */
